HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 370

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI)
requested if SCTDR does not contain new transmit data when the MSB is transmitted.
Bit 2: TEIE
0
1
Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register
Bits 1 and 0—Clock Enable 1 and 0 (CKE1 and CKE0): These bits select the SCI clock source
and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and
CKE0, the SCK pin can be used for serial clock output or serial clock input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). Before selecting the SCI operating mode in the serial mode
register (SCSMR), set CKE1 and CKE0. For further details on selection of the SCI clock source,
see table 13.9 in section 13.3, Operation.
Bit 1:
CKE1
0
1
Notes: 1. The output clock frequency is the same as the bit rate.
350
(SCSSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end
(TEND) bit to 0, or by clearing the TEIE bit to 0.
Bit 0:
CKE0 Description
0
1
0
1
2 The input clock frequency is 16 times the bit rate.
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Description
Transmit-end interrupt (TEI) requests are disabled.*
Transmit-end interrupt (TEI) requests are enabled.*
Internal clock, SCK pin used for input pin (input signal is
ignored)
Internal clock, SCK pin used for serial clock output
Internal clock, SCK pin used for clock output*
Internal clock, SCK pin used for serial clock output
External clock, SCK pin used for clock input*
External clock, SCK pin used for serial clock input
External clock, SCK pin used for clock input*
External clock, SCK pin used for serial clock input
2
2
1
(Initial value)
(Initial value)
(Initial value)