HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 282

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Burst Write: The timing chart for a burst write is shown in figure 10.27. In the SH7708 Series, a
burst write occurs only in the event of cache copy-back. In a burst write operation, following the
Tr cycle in which ACTV command output is performed, a WRIT command is issued in the Tc1,
Tc2, and Tc3 cycles, and a WRITA command that performs auto-precharge is issued in the Tc4
cycle. In the write cycle, the write data is output at the same time as the write command. For the
write with auto-precharge command, precharging of the relevant bank is performed in the
synchronous DRAM after completion of the write command, and therefore no command can be
issued for the same bank until precharging is completed. Consequently, in addition to the
precharge wait cycle, Tpc, used in a read access, cycle Trwl is added as a wait interval until
precharging is started, following the write command. Issuance of a new command for the same
bank is postponed during this interval. The number of Trwl cycles can be specified by the TRWL
bit in MCR.
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