HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 366

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In synchronous
mode, the data length is always 8 bits, regardless of the CHR setting.
Bit 6: CHR
0
1
Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data, in asynchronous mode. In synchronous mode, a parity bit is neither added
nor checked, regardless of the PE setting.
Bit 5: PE
0
1
Bit 4—Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked. The
O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1
to enable parity addition and checking. The O/E setting is ignored in synchronous mode, and in
asynchronous mode when parity addition and checking is disabled.
Bit 4: O/E
0
1
346
Description
8-bit data
7-bit data. (When 7-bit data is selected, the MSB (bit 7) of the transmit
data register is not transmitted.)
Description
Parity bit not added or checked
Parity bit added and checked. When PE is set to 1, an even or odd
parity bit is added to transmit data, depending on the parity mode (O/E)
setting. Receive data parity is checked according to the even/odd (O/E)
mode setting.
Description
Even parity
If even parity is selected, the parity bit is added to transmit data to make
an even number of 1s in the transmitted character and parity bit
combined. Receive data is checked to see if it has an even number of
1s in the received character and parity bit combined.
Odd parity
If odd parity is selected, the parity bit is added to transmit data to make
an odd number of 1s in the transmitted character and parity bit
combined. Receive data is checked to see if it has an odd number of 1s
in the received character and parity bit combined.
(Initial value)
(Initial value)
(Initial value)