HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 363

IC SUPERH MPU ROMLESS 144LQFP

HD6417708SF60

Manufacturer Part Number
HD6417708SF60
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417708SF60

Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-

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13.1.3
The SCI has the serial pins summarized in table 13.1.
Table 13.1 SCI Pins
Pin Name
Serial clock pin
Receive data pin
Transmit data pin
Note: These pins function as mode input pins MD0–MD02 after a power-on reset. They are made
13.1.4
Table 13.2 summarizes the SCI internal registers. These registers select the communication mode
(asynchronous or synchronous), specify the data format and bit rate, and control the transmitter
and receiver sections.
Table 13.2 Registers
Name
Serial mode register
Bit rate register
Serial control register
Transmit data register
Serial status register
Receive data register
Serial port register
Notes: 1 Only 0 can be written, to clear the flags.
to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and
CKE0 bits in SCSCR and the C/A bit in SCSMR. Break status transmission and detection
can be performed by means of the SCI’s SCSPTR register.
2 Initialized by power-on reset or manual reset.
3. All bits except 2 and 0 are initialized to 0. The value of bits 2 and 0 is undefined.
Pin Configuration
Register Configuration
Abbreviation Input/Output
SCK
RxD
TxD
Abbreviation
SCSMR
SCBRR
SCSCR
SCTDR
SCSSR
SCRDR
SCSPTR
Input/output
Input
Output
R/W
R/W
R/W
R/W
R/W
R/(W)*
R
R/W
1
Initial Value*
H'00
H'FF
H'00
H'FF
H'84
H'00
Undefined
(Initialized)*
Function
Clock input/output
Receive data input
Transmit data output
3
2
Address
H'FFFFFE80
H'FFFFFE82
H'FFFFFE84
H'FFFFFE86
H'FFFFFE88
H'FFFFFE8A 8
H'FFFFFF7C 8
Access Size
8
8
8
8
8
343

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