HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 90

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

3.5
There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial
page write.
3.5.1
A TLB miss results when the virtual address and the address array of the selected TLB entry are
compared and no match is found. TLB miss exception handling includes both hardware and
software operations.
Hardware Operations: In a TLB miss, the SH7708 Series hardware executes a set of prescribed
operations, as follows:
1. The VPN field of the virtual address causing the exception is written to the PTEH register.
2. The virtual address causing the exception is written to the TEA register.
3. Either exception code H'040 for a load access, or H'060 for a store access, is written to the
4. The PC value indicating the address of the instruction in which the exception occurred is
5. The contents of the status register (SR) at the time of the exception are written to the save
6. The mode (MD) bit in SR is set to 1 to place the SH7708 Series in privileged mode.
7. The block (BL) bit in SR is set to 1 to mask any further exception requests.
8. The register bank (RB) bit in SR is set to 1.
9. The RC field in the MMU control register (MMUCR) is incremented by 1 when all entries
10. Execution branches to the address obtained by adding the value of the VBR contents and
Software (TLB Miss Handler) Operations: The software searches the page tables in external
memory and allocates the required page table entry. Upon retrieving the required page table entry,
the software must execute the following operations:
1. Write the value of the physical page number (PPN) field and the protection key (PR), page size
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EXPEVT register.
written to the save program counter (SPC). If the exception occurred in a delay slot, the PC
value indicating the address of the related delayed branch instruction is written to the SPC.
status register (SSR).
indexed are valid. When some entries indexed are invalid, the smallest way number of them is
set in RC.
H'00000400 to invoke the user-written TLB miss exception handler.
(SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table entry
recorded in the address translation table in external memory into the PTEL register in the
SH7708 Series.
MMU Exceptions
TLB Miss Exception