HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 447

IC SUPERH MPU ROMLESS 144LQFP

HD6417708SF60

Manufacturer Part Number
HD6417708SF60
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417708SF60

Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-

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15.1.4
Table 15.3 shows the configuration of the two registers of the 8-bit general-purpose I/O port
(PCTR and PDTR) and the one register of the SCI I/O port (SCSPTR).
Table 15.3 Register Configuration
Register
Port control register
Port data register
Serial port register
Notes: 1. Initialized by a power-on reset.
15.2
15.2.1
The port control register (PCTR) is a 16-bit read/write register that controls the input/output
direction and pull-up for each bit in the 8-bit port. As the initial value of the port data register
(PDR) is undefined, all the bits in the 8-bit port should be set to output with PCTR after writing a
value to the PDTR register.
PCTR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in
standby mode, and retains its contents.
Initial value:
Initial value:
2. Bits other than 2 and 0 are initialized to H'00. Bits 2 and 0 are undefined.
Bit name:
Bit name:
Register Configuration
Register Descriptions
Port Control Register (PCTR)
R/W:
R/W:
Bit:
Bit:
PUP
PUP
PB7
R/W
PB3
R/W
15
0
7
0
Symbol
PCTR
PDTR
SCSPTR
PB7
R/W
PB3
R/W
14
IO
IO
0
6
0
R/W
R/W
R/W
R/W
PUP
PUP
PB6
R/W
PB2
R/W
13
0
5
0
Initial Value*
H'0000
Undefined
*
2
PB6
R/W
PB2
R/W
12
IO
IO
0
4
0
PUP
PUP
PB5
R/W
PB1
R/W
1
11
0
3
0
Address
H'FFFFFF76
H'FFFFFF78
H'FFFFFF7C
PB5
R/W
PB1
R/W
10
IO
IO
0
2
0
PUP
PUP
PB4
R/W
PB0
R/W
9
0
1
0
Access Size
16
8
8
PB4
R/W
PB0
R/W
IO
IO
8
0
0
0
427

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