ST92F150JDV1QC STMicroelectronics, ST92F150JDV1QC Datasheet - Page 136

• Manufacturer Part Number: ST92F150JDV1QC
• Description: IC MCU 128K FLASH 100-PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150JDV1QC

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2137

ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK CONTROL REGISTERS (Cont’d)
PLL CONFIGURATION REGISTER (PLLCONF)
R246 - Read/Write
Register Page: 55
Reset Value: 0x00 x111
Bit 7 = FREEN: PLL Free Running Mode Enable
0: PLL Free Running Mode disabled
1: PLL Free Running Mode enabled
When this bit is set, even if the DX[2:0] bits are all
set to 1, the PLL is not stopped but provides a slow
frequency back-up clock, selectable by the
CSU_CKSEL bit of the CLK_FLAG register (with-
out needing to have the LOCK bit equal to ‘1’).
Bits 5:4 = MX[1:0]: PLL Multiplication Factor.
Refer to
WARNING: After these bits are modified, take
care that the PLL lock-in time has elapsed before
setting the CSU_CKSEL bit in the CLK_FLAG reg-
ister.
Bits 2:0 = DX[2:0]: PLL output clock divider factor.
Refer to
136/429
9
FREEN
7
Table 29
Table 30
0
MX1
for multiplier settings.
for divider settings.
MX0
0
DX2
DX1
DX0
0
Table 29. PLL Multiplication Factors
Table 30. PLL Divider Factors
DX2
0
0
0
0
1
1
1
1
MX1
1
0
1
0
DX1
0
0
1
1
0
0
1
1
MX0
0
0
1
1
DX0
0
1
0
1
0
1
0
1
(PLL OFF, Reset State)
PLL CLOCK/1
PLL CLOCK/2
PLL CLOCK/3
PLL CLOCK/4
PLL CLOCK/5
PLL CLOCK/6
PLL CLOCK/7
CLOCK2 x
CLOCK2
CK
14
10
8
6