ST92F150JDV1QC STMicroelectronics, ST92F150JDV1QC Datasheet - Page 229

• Manufacturer Part Number: ST92F150JDV1QC
• Description: IC MCU 128K FLASH 100-PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150JDV1QC

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2137

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
INTERRUPT MASK REGISTER (IMR)
R246 - Read/Write
Reset value: 0xx00000
Bit 7 = BSN: Buffer or shift register empty inter-
rupt.
This bit selects the source of the transmitter regis-
ter empty interrupt.
0: Select a Shift Register Empty as source of a
1: Select a Buffer Register Empty as source of a
Bit 6 = RXEOB: Received End of Block.
This bit is set by hardware only and must be reset
by software. RXEOB is set after a receiver DMA
cycle to mark the end of a data block.
0: Clear the interrupt request.
1: Mark the end of a received block of data.
Bit 5 = TXEOB: Transmitter End of Block.
This bit is set by hardware only and must be reset
by software. TXEOB is set after a transmitter DMA
cycle to mark the end of a data block.
0: Clear the interrupt request.
1: Mark the end of a transmitted block of data.
BSN
Transmitter Register Empty interrupt.
Transmitter Register Empty interrupt.
7
RXEOB TXEOB
RXE
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
RXA
RXB
RXDI
TXDI
0
Bit 4 = RXE: Receiver Error Mask.
0: Disable Receiver error interrupts (OE, PE, and
1: Enable Receiver error interrupts.
Bit 3 = RXA: Receiver Address Mask.
0: Disable Receiver Address interrupt (RXAP
1: Enable Receiver Address interrupt.
Bit 2 = RXB: Receiver Break Mask.
0: Disable Receiver Break interrupt (RXBP pend-
1: Enable Receiver Break interrupt.
Bit 1 = RXDI: Receiver Data Interrupt Mask.
0: Disable Receiver Data Pending and Receiver
1: Enable Receiver Data Pending and Receiver
Note: RXDI has no effect on DMA transfers.
Bit 0 = TXDI: Transmitter Data Interrupt Mask.
0: Disable Transmitter Buffer Register Empty,
1: Enable Transmitter Buffer Register Empty,
Note: TXDI has no effect on DMA transfers.
FE pending bits in the S_ISR register).
pending bit in the S_ISR register).
ing bit in the S_ISR register).
End of Block interrupts (RXDP and RXEOB
pending bits in the S_ISR register).
End of Block interrupts.
Transmitter Shift Register Empty, or Transmitter
End of Block interrupts (TXBEM, TXSEM, and
TXEOB bits in the S_ISR register).
Transmitter Shift Register Empty, or Transmitter
End of Block interrupts.
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