ST92F150JDV1QC STMicroelectronics, ST92F150JDV1QC Datasheet - Page 265

• Manufacturer Part Number: ST92F150JDV1QC
• Description: IC MCU 128K FLASH 100-PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150JDV1QC

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2137

I
Figure 127. I
Any transfer can be done using either the I
registers directly or via the DMA.
If the transfer is to be done directly by accessing
the I2CDR, the interface waits (by holding the SCL
line low) for software to write in the Data Register
before transmission of a data byte, or to read the
Data Register after a data byte is received.
If the transfer is to be done via DMA, the interface
sends a request for a DMA transfer. Then it waits
for the DMA to complete. The transfer between the
interface and the I
rising edge of the SCL clock.
The SCL frequency (F
mode is controlled by a programmable clock divid-
er. The speed of the I
between Standard (0-100KHz) and Fast (100-
400KHz) I
10.8.4 I
To enable the interface in I
bit must be set twice as the first write only acti-
vates the interface (only the PE bit is set); and the
bit7 of I2CCR register must be cleared.
The I
(the M/SL bit is cleared) except when it initiates a
transmission or a receipt sequencing (master
mode).
2
C BUS INTERFACE (Cont’d)
2
C interface always operates in slave mode
2
C State Machine
2
C modes.
SCL
SDA
2
C BUS Protocol
CONDITION
START
2
C bus will begin on the next
2
C interface may be selected
scl
) generated in master
2
C mode the I2CCR.PE
MSB
1
2
2
C
The multimaster function is enabled with an auto-
matic switch from master mode to slave mode
when the interface loses the arbitration of the I
bus.
10.8.4.1 I
As soon as a start condition is detected, the
address word is received from the SDA line and
sent to the shift register; then it is compared with
the address of the interface or the General Call
address (if selected by software).
Note: In 10-bit addressing mode, the comparison
includes the header sequence (11110xx0) and the
two most significant bits of the address.
■
■
■
Header (10-bit mode) or Address (both 10-bit
and 7-bit modes) not matched: the state
machine is reset and waits for another Start
condition.
Header matched (10-bit mode only): the
interface generates an acknowledge pulse if the
ACK bit of the control register (I2CCR) is set.
Address matched: the I2CSR1.ADSL bit is set
and an acknowledge bit is sent to the master if
the I2CCR.ACK bit is set. An interrupt request
occurs if the I2CCR.ITE bit is set. Then the SCL
line is held low until the microcontroller reads
the I2CSR1 register (see
sequencing EV1).
8
2
C Slave Mode
ACK
9
CONDITION
I2C BUS INTERFACE
STOP
Figure 128
VR02119B
Transfer
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2
9
C