ST92F150JDV1QC STMicroelectronics, ST92F150JDV1QC Datasheet - Page 368

• Manufacturer Part Number: ST92F150JDV1QC
• Description: IC MCU 128K FLASH 100-PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150JDV1QC

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2137

10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
REGISTER DESCRIPTION (Cont’d)
CHANNEL 8 DATA HIGH REGISTER (D8HR)
R240 - Read/Write
Register Page: 62
Reset Value: undefined
Bits 7:0 = D8.[9:2]: Channel 8 9:2 bit Data
CHANNEL 8 DATA LOW REGISTER (D8LR)
R241 - Read/Write
Register Page: 62
Reset Value: xx00 0000
Bits 7:6 = D8.[1:0]: Channel 8 1:0 bit Data
Bits 5:0 = Reserved, forced by hardware to 0.
CHANNEL 9 DATA HIGH REGISTER (D9HR)
R242 - Read/Write
Register Page: 62
Reset Value: undefined
Bits 7:0 = D9.[9:2]: Channel 9 9:2 bit Data
CHANNEL 9 DATA LOW REGISTER (D9LR)
R243 - Read/Write
Register Page: 62
Reset Value: xx00 0000
Bits 7:0 = D9.[1:0]: Channel 9 1:0 bit Data
Bits 5:0 = Reserved, forced by hardware to 0.
368/429
9
D8.9 D8.8 D8.7
D8.1 D8.0
D9.9 D9.8 D9.7
D9.1 D9.0
7
7
7
7
0
0
D8.6 D8.5 D8.4 D8.3 D8.2
D9.6 D9.5 D9.4 D9.3 D9.2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHANNEL 10 DATA HIGH REGISTER (D10HR)
R244 - Read/Write
Register Page: 62
Reset Value: undefined
Bits 7:0 = D10.[9:2]: Channel 10 9:2 bit Data
CHANNEL 10 DATA LOW REGISTER (D10LR)
R245 - Read/Write
Register Page: 62
Reset Value: xx00 0000
Bits 7:0 = D10.[1:0]: Channel 10 1:0 bit Data
Bits 5:0 = Reserved, forced by hardware to 0.
CHANNEL 11 DATA HIGH REGISTER (D11HR)
R246 - Read/Write
Register Page: 62
Reset Value: undefined
Bits 7:0 = D11.[9:2]: Channel 11 9:2 bit Data
CHANNEL 11 DATA LOW REGISTER (D11LR)
R247 - Read/Write
Register Page: 62
Reset Value: xx00 0000
Bits 7:0 = D11.[1:0]: Channel 11 1:0 bit Data
Bits 5:0 = Reserved, forced by hardware to 0.
D10.9 D10.8 D10.7 D10.6 D10.5 D10.4 D10.3 D10.2
D10.1 D10.0
D11.9 D11.8 D11.7 D11.6 D11.5 D11.4 D11.3 D11.2
D11.1 D11.0
7
7
7
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0