ST92F150JDV1QC STMicroelectronics, ST92F150JDV1QC Datasheet - Page 372

• Manufacturer Part Number: ST92F150JDV1QC
• Description: IC MCU 128K FLASH 100-PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150JDV1QC

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2137

10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
REGISTER DESCRIPTION (Cont’d)
CONTROL LOGIC REGISTER 1 (CLR1)
R252 - Read/Write
Register Page: 63
Reset Value: 0000 1111 (0Fh)
Bits 7:4 = SC[3:0]: Start Conversion Channel
These four bits define the starting analog input
channel (Autoscan Mode). The first channel ad-
dressed by SC[3:0] is converted, then the channel
number is incremented for the successive conver-
sion, until channel 15 (1111) is converted. When
SC3, SC2, SC1 and SC0 are all set, only channel
15 will be converted.
Bits 3:0 = CC[3:0]: Compare Channels
The programmed value corresponds to the first of
the two adjacent channels (A) on which it is possi-
ble to define a level window for the converted ana-
log input (see
Note: If a write access to this register occurs, the
conversion is re-started from the SC[3:0] channel.
Table 68. Compare Channels definition
Table 69. Prescaler programming
372/429
9
PR[2:0]
SC3
7
000
001
010
011
100
101
110
111
CC[3:0]
0000
0001
0010
0011
SC2
T
T
A/D clock
INTCLK
10
12
14
16
SC1
2
4
6
8
Table
Channel A
/
SC0
68).
15
0
1
2
(MHz)
f
4.00
2.00
1.33
1.00
0.80
0.66
0.57
0.50
ADC
@T
CC3
INTCLK
CC2
T
Channel B
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Sample
(µs)
= 8MHz
2
4
6
8
CC1
0
1
2
3
T
(µs)
Conv
14
21
28
7
CC0
0
(MHz)
10.00
f
5.00
3.33
2.50
2.00
1.66
1.43
1.25
ADC
@T
Table 68. Compare Channels definition
CONTROL LOGIC REGISTER 2 (CLR2)
R253 - Read/Write
Register Page: 63
Reset Value: 1010 0000 (A0h)
Bits 7:5 = PR[2:0]: INTCLK Frequency Prescaler
These bits determine the ratio between the ADC
clock and the system clock (INTCLK) according to
Table
PR2
7
INTCLK
CC[3:0]
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
69.
T
PR1
Sample
Not Allowed
Not Allowed
(µs)
= 20MHz
2.4
3.2
4.8
5.6
6.4
4
PR0 EXTG INTG POW CONT
T
11.2
16.8
19.6
22.4
(µs)
8.4
Conv
14
Channel A
10
11
12
13
14
3
4
5
6
7
8
9
(MHz)
12.00
f
6.00
2.00
1.71
1.50
4.00
3.00
2.40
ADC
@T
INTCLK
Channel B
T
Not Allowed
Not Allowed
Sample
2.66
3.33
4.66
5.33
(µs)
=24MHz
4
2
10
11
12
13
14
15
4
5
6
7
8
9
T
11.66
16.33
18.66
9.33
(µs)
Conv
ST
14
0
7