ST92F150JDV1QC STMicroelectronics, ST92F150JDV1QC Datasheet - Page 346

• Manufacturer Part Number: ST92F150JDV1QC
• Description: IC MCU 128K FLASH 100-PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150JDV1QC

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2137

CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
CAN RECEIVE FIFO REGISTERS (CRFRx)
Read / Write
Reset Value: 0000 0000 (00h)
Note: To clear a bit in this register, software must
write a “1” to the bit.
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = RFOM Release FIFO Output Mailbox
- Read/Set
Set by software to release the output mailbox of
the FIFO. The output mailbox can only be released
when at least one message is pending in the FIFO.
Setting this bit when the FIFO is empty has no ef-
fect. If at least two messages are pending in the
FIFO, the software has to release the output mail-
box to access the next message.
Cleared by hardware when the output mailbox has
been released.
Bit 4 = FOVR FIFO Overrun
- Read/Clear
This bit is set by hardware when a new message
has been received and passed the filter while the
FIFO was full.
This bit is cleared by software.
Bit 3 = FULL FIFO Full
- Read/Clear
Set by hardware when three messages are stored
in the FIFO.
This bit is cleared by software.
Bit 2 = Reserved. Forced to 0 by hardware.
Bit 1:0 = FMP[1:0] FIFO Message Pending
- Read
These bits indicate how many messages are
pending in the receive FIFO.
FMP is increased each time the hardware stores a
new message in to the FIFO. FMP is decreased
each time the software releases the output mail-
box by setting the RFOM bit.
346/429
9
7
0
0
RFOM FOVR
FULL
0
FMP1 FMP0
0
CAN INTERRUPT ENABLE REGISTER (CIER)
All bits of this register are set and cleared by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = WKUIE Wake-Up Interrupt Enable
0: No interrupt when WKUI is set.
1: Interrupt generated when WKUI bit is set.
Bit 6 = FOVIE1 FIFO Overrun Interrupt Enable
0: No interrupt when FOVR is set.
1: Interrupt generation when FOVR is set.
Bit 5 = FFIE1 FIFO Full Interrupt Enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
Bit 4 = FMPIE1 FIFO Message Pending Interrupt
Enable
0: No interrupt on FMP[1:0] bits transition from 00b
1: Interrupt generated on FMP[1:0] bits transition
Bit 3 = FOVIE0 FIFO Overrun Interrupt Enable
0: No interrupt when FOVR bit is set.
1: Interrupt generated when FOVR bit is set.
Bit 2 = FFIE0 FIFO Full Interrupt Enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
Bit 1 = FMPIE0 FIFO Message Pending Interrupt
Enable
0: No interrupt on FMP[1:0] bits transition from 00b
1: Interrupt generated on FMP[1:0] bits transition
Bit 0 = TMEIE Transmit Mailbox Empty Interrupt
Enable
0: No interrupt when RQCPx bit is set.
1: Interrupt generated when RQCPx bit is set.
Note: refer to Standard Interrupts Section.
WKUIE FOVIE1
to 01b.
from 00b to 01b.
to 01b.
from 00b to 01b.
7
FFIE1
FMPIE1 FOVIE0
FFIE0
FMPIE0
TMEIE
0