MC68HC908GP32CB Freescale Semiconductor, MC68HC908GP32CB Datasheet - Page 112

• Manufacturer Part Number: MC68HC908GP32CB
• Description: IC MCU 32K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Low-Voltage Inhibit (LVI)
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See
Functional Description
remains in reset until V
14.3.2.5 Low-Voltage Inhibit (LVI) Reset
output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
11.3.1 Polled LVI Operation
In applications that can operate at V
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be at logic 0 to enable the LVI
module, and the LVIRSTD bit must be at logic 1 to disable LVI resets.
11.3.2 Forced Reset Operation
In applications that require V
module to reset the MCU when V
LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets.
112
Addr.
$FE0C LVI Status Register (LVISR)
Register Name
FROM CONFIG1
DETECTOR
LOW V
LVI5OR3
for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU
DD
V
DD
DD
rises above a voltage, V
Reset:
Read:
Write:
DD
Figure 11-1. LVI Module Block Diagram
Figure 11-2. LVI I/O Register Summary
to remain above the V
V
V
DD
DD
DD
FROM CONFIG
LVIOUT
Bit 7
> LVI
≤ LVI
DD
MC68HC908GP32 Data Sheet, Rev. 10
LVIPWRD
0
falls below the V
levels below the V
Trip
Trip
for details of the interaction between the SIM and the LVI. The
= Unimplemented
= 1
= 0
6
0
0
LVIOUT
TRIPR
TRIPF
TRIPF
5
0
0
STOP INSTRUCTION
FROM CONFIG1
, which causes the MCU to exit reset. See
TRIPF
LVIRSTD
level. In the configuration register, the
level, enabling LVI resets allows the LVI
level, software can monitor V
4
0
0
3
0
0
FROM CONFIG1
LVISTOP
LVI RESET
2
0
0
Freescale Semiconductor
1
0
0
DD
by polling
6.2
Bit 0
0
0