MC68HC908GP32CB Freescale Semiconductor, MC68HC908GP32CB Datasheet - Page 64

• Manufacturer Part Number: MC68HC908GP32CB
• Description: IC MCU 32K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Clock Generator Module (CGM)
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,
CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The
loop filter then slightly alters the DC voltage on the external capacitor connected to CGM/XFC based on
the width and direction of the correction pulse. The filter can make fast or slow corrections depending on
its mode, described in
reference frequency determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency, f
this comparison.
5.3.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
5.3.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
Automatic mode is recommended for most users.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See
Bandwidth Control
request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit
continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is
set, the VCO clock is safe to use as the source for the base clock. (See
If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the application. (See
Interrupts
The following conditions apply when the PLL is in automatic bandwidth control mode:
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Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in
the PLL bandwidth control register. (See
Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. (See
tracking mode when not in acquisition mode or when the ACQ bit is set.
The ACQ bit (See
the filter. (See
The ACQ bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See
more information.)
The LOCK bit is a read-only indicator of the locked state of the PLL.
for information and precautions on using interrupts.)
Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt
5.3.4 Acquisition and Tracking
RDV
5.3.4 Acquisition and Tracking
5.5.2 PLL Bandwidth Control
. The circuit determines the mode of the PLL and the lock condition based on
MC68HC908GP32 Data Sheet, Rev. 10
5.3.8 Base Clock Selector
5.5.2 PLL Bandwidth Control
Modes.)
Modes. The value of the external capacitor and the
Register.) is a read-only indicator of the mode of
5.8 Acquisition/Lock Time Specifications
Circuit.) The PLL is automatically in
5.3.8 Base Clock Selector
Register.)
Freescale Semiconductor
5.5.2 PLL
Circuit.)
for
5.6