MC68HC908GP32CB Freescale Semiconductor, MC68HC908GP32CB Datasheet - Page 81

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MC68HC908GP32CB

Manufacturer Part Number
MC68HC908GP32CB
Description
IC MCU 32K FLASH 8MHZ 42-SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908GP32CB

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
For Use With
M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Chapter 6
Configuration Register (CONFIG)
6.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers
enable or disable these options:
6.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can
be written once after each reset. All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU, it is recommended that these registers be written
immediately after reset. The configuration registers are located at $001E and $001F. The configuration
register may be read at anytime.
Freescale Semiconductor
Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles)
COP timeout period (262,128 or 8176 CGMXCLK cycles)
STOP instruction
Computer operating properly module (COP)
Low-voltage inhibit (LVI) module control and voltage trip point selection
Enable/disable the oscillator (OSC) during stop mode
Address:
Reset:
On a FLASH device, the options except LVI5OR3 are one-time writeable
by the user after each reset. The LVI5OR3 bit is one-time writeable by the
user only after each POR (power-on reset). The CONFIG registers are not
in the FLASH memory but are special registers containing one-time
writeable latches after each reset. Upon a reset, the CONFIG registers
default to predetermined settings as shown in
Read:
Write:
Bit 7
$001E
0
0
Figure 6-1. Configuration Register 2 (CONFIG2)
= Unimplemented
6
0
0
MC68HC908GP32 Data Sheet, Rev. 10
5
0
0
NOTE
4
0
0
3
0
0
Figure 6-1
2
0
0
and
OSCSTOPENB SCIBDSRC
Figure
1
0
6-2.
Bit 0
0
81

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