MC68HC908GP32CB Freescale Semiconductor, MC68HC908GP32CB Datasheet - Page 113

• Manufacturer Part Number: MC68HC908GP32CB
• Description: IC MCU 32K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V
V
continually entering and exiting reset if V
V
11.3.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5-V or 3-V
protection.
11.4 LVI Status Register
The LVI status register (LVISR) indicates if the V
LVIOUT — LVI Output Bit
11.5 LVI Interrupts
The LVI module does not generate interrupt requests.
Freescale Semiconductor
DD
TRIPF
This read-only flag becomes set when the V
(See
rises above the rising trip point voltage, V
by the hysteresis voltage, V
Table
Address:
11-1.) Reset clears the LVIOUT bit.
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (V
Chapter 19 Electrical Specifications
Reset:
Read:
Write:
LVIOUT
$FE0C
Bit 7
0
= Unimplemented
Figure 11-3. LVI Status Register (LVISR)
V
TRIPF
TRIPF
6
0
0
V
Table 11-1. LVIOUT Bit Indication
V
HYS
DD
MC68HC908GP32 Data Sheet, Rev. 10
DD
< V
[5 V] or V
V
> V
< V
.
DD
DD
DD
DD
TRIPR
TRIPF
< V
5
0
0
fall below V
is approximately equal to V
TRIPR
TRIPR
TRIPF
DD
NOTE
DD
voltage falls below the V
for the actual trip point voltages.)
4
0
0
. This prevents a condition in which the MCU is
voltage was detected below the V
[3 V]) may be lower than this. (See
TRIPF
Previous value
), the LVI will maintain a reset condition until
3
0
0
LVIOUT
0
1
2
0
0
TRIPF
TRIPF
. V
1
0
0
TRIPR
trip voltage.
is greater than
TRIPF
Bit 0
LVI Status Register
0
0
level.
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