MC68HC908GP32CB Freescale Semiconductor, MC68HC908GP32CB Datasheet - Page 197

• Manufacturer Part Number: MC68HC908GP32CB
• Description: IC MCU 32K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

TBR2:TBR0 — Timebase Rate Selection
TACK — Timebase ACKnowledge
TBIE — Timebase Interrupt Enabled
TBON — Timebase Enabled
16.5 Interrupts
The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2:TBR0. When
the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt request.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
Freescale Semiconductor
These read/write bits are used to select the rate of timebase interrupts as shown in
The TACK bit is a write-only bit and always reads as 0. Writing a logic 1 to this bit clears TBIF, the
timebase interrupt flag bit. Writing a logic 0 to this bit has no effect.
This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the
TBIE bit.
This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption
when its function is not necessary. The counter can be initialized by clearing and then setting this bit.
Reset clears the TBON bit.
1 = Clear timebase interrupt flag
0 = No effect
1 = Timebase interrupt enabled
0 = Timebase interrupt disabled
1 = Timebase enabled
0 = Timebase disabled and the counter initialized to 0s
Do not change TBR2:TBR0 bits while the timebase is enabled
(TBON = 1).
TBR2
0
0
0
0
1
1
1
1
Table 16-1. Timebase Rate Selection for OSC1 = 32.768-kHz
TBR1
0
0
1
1
0
0
1
1
MC68HC908GP32 Data Sheet, Rev. 10
TBR0
0
1
0
1
0
1
0
1
Divider
32768
8192
2048
NOTE
128
64
32
16
8
1024
2048
4096
Timebase Interrupt Rate
256
512
Hz
16
1
4
~0.24
1000
~ 3.9
62.5
~0.5
250
ms
~2
~1
Table
16-1.
Interrupts
197