MC68HC908GP32CB Freescale Semiconductor, MC68HC908GP32CB Datasheet - Page 127

• Manufacturer Part Number: MC68HC908GP32CB
• Description: IC MCU 32K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.5.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the eight port D pins. Each bit is individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRD is configured for output mode.
PTDPUE7–PTDPUE0 — Port D Input Pullup Enable Bits
12.6 Port E
Port E is a 2-bit special-function port that shares two of its pins with the serial communications interface
(SCI) module.
12.6.1 Port E Data Register
The port E data register contains a data latch for each of the two port E pins.
PTE1 and PTE0 — Port E Data Bits
Freescale Semiconductor
These writable bits are software programmable to enable pullup devices on an input port bit.
PTE1 and PTE0 are read/write, software programmable bits. Data direction of each port E pin is under
the control of the corresponding bit in data direction register E.
1 = Corresponding port D pin configured to have internal pullup
0 = Corresponding port D pin has internal pullup disconnected
Alternate Function:
Address:
Address:
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. See
Reset:
Read:
Write:
Reset:
Read:
Write:
Figure 12-16. Port D Input Pullup Enable Register (PTDPUE)
PTDPUE7
$000F
Bit 7
$0008
0
Bit 7
0
PTDPUE6
Figure 12-17. Port E Data Register (PTE)
= Unimplemented
6
0
MC68HC908GP32 Data Sheet, Rev. 10
6
0
PTDPUE5
5
0
Table
5
0
PTDPUE4
NOTE
12-6.
4
0
Unaffected by reset
4
0
PTDPUE3
3
0
3
0
PTDPUE2
2
0
2
0
PTDPUE1
1
0
PTE1
RxD
1
PTDPUE0
Bit 0
0
PTE0
Bit 0
TxD
Port E
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