MC68HC908GP32CB Freescale Semiconductor, MC68HC908GP32CB Datasheet - Page 76

• Manufacturer Part Number: MC68HC908GP32CB
• Description: IC MCU 32K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Clock Generator Module (CGM)
5.5.6 PLL Reference Divider Select Register
The PLL reference divider select register (PMDS) contains the programming information for the modulo
reference divider.
RDS3–RDS0 — Reference Divider Select Bits
Bit7–Bit4 — Unimplemented Bits
5.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU
interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL)
enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether
76
PCTL is set. (See
register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See
Clock Selector Circuit
$40 for a default range multiply value of 64.
These read/write bits control the modulo reference divider that selects the reference division factor, R.
(See
PLLON bit in the PCTL is set. A value of $00 in the reference divider select register configures the
reference divider the same as a value of $01. (See
initializes the register to $01 for a default divide value of 1.
These bits have no function and always read as 0s.
5.3.3 PLL Circuits
Address:
The VCO range select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
PMDS may be called PRDS on other HC08 derivatives.
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
The default divide value of 1 is recommended for all applications.
Reset:
Read:
Write:
Figure 5-9. PLL Reference Divider Select Register (PMDS)
5.3.7 Special Programming
$003B
Bit 7
0
0
and
and
5.3.7 Special Programming
= Unimplemented
5.3.6 Programming the
6
0
0
MC68HC908GP32 Data Sheet, Rev. 10
5
0
0
NOTE
NOTE
NOTE
NOTE
Exceptions.) A value of $00 in the VCO range select
4
0
0
5.3.7 Special Programming
PLL.) RDS7–RDS0 cannot be written when the
Exceptions.). Reset initializes the register to
RDS3
3
0
RDS2
2
0
RDS1
1
0
Exceptions.) Reset
Freescale Semiconductor
RDS0
Bit 0
1
5.3.8 Base