MC68HC908GP32CB Freescale Semiconductor, MC68HC908GP32CB Datasheet - Page 74

• Manufacturer Part Number: MC68HC908GP32CB
• Description: IC MCU 32K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Clock Generator Module (CGM)
AUTO — Automatic Bandwidth Control Bit
LOCK — Lock Indicator Bit
ACQ — Acquisition Mode Bit
5.5.3 PLL Multiplier Select Register High
The PLL multiplier select register high (PMSH) contains the programming information for the high byte of
the modulo feedback divider.
MUL11–MUL8 — Multiplier Select Bits
74
This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual
operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK,
is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0
and has no meaning. The write one function of this bit is reserved for test, so this bit must always be
written a 0. Reset clears the LOCK bit.
When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode
or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is
in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is
stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
These read/write bits control the high byte of the modulo feedback divider that selects the VCO
frequency multiplier N. (See
1 = Automatic bandwidth control
0 = Manual bandwidth control
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
1 = Tracking mode
0 = Acquisition mode
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 5-6. PLL Multiplier Select Register High (PMSH)
$0037
AUTO
$0038
Bit 7
Bit 7
Figure 5-5. PLL Bandwidth Control Register (PBWC)
0
0
0
= Unimplemented
= Unimplemented
5.3.3 PLL Circuits
LOCK
6
0
6
0
0
MC68HC908GP32 Data Sheet, Rev. 10
ACQ
5
0
5
0
0
and
R
4
0
0
4
0
0
5.3.6 Programming the
= Reserved
MUL11
3
0
0
3
0
MUL10
2
0
0
2
0
MUL9
PLL.) A value of $0000 in
1
0
0
1
0
Freescale Semiconductor
MUL8
Bit 0
Bit 0
R
0
0