LFXP2-30E-5FN484C LATTICE SEMICONDUCTOR, LFXP2-30E-5FN484C Datasheet - Page 28

• Manufacturer Part Number: LFXP2-30E-5FN484C
• Description: IC, LATTICEXP2 FPGA, 435MHZ, FPBGA-484
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeXP2r

Specifications of LFXP2-30E-5FN484C

• No. Of Logic Blocks: 29000
• No. Of Macrocells: 14500
• Family Type: LatticeXP2
• No. Of Speed Grades: 5
• No. Of I/o's: 363
• Clock Management: PLL
• Total Ram Bits: 387Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
IPexpress™
The user can access the sysDSP block via the ispLEVER IPexpress tool, which provides the option to configure
each DSP module (or group of modules), or by direct HDL instantiation. In addition, Lattice has partnered with The
MathWorks
ispLEVER to dramatically shorten the DSP design cycle in Lattice FPGAs.
Optimized DSP Functions
Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeXP2 DSP
include the Bit Correlator, FFT functions, FIR Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/Decoder and
Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available DSP IP cores.
Resources Available in the LatticeXP2 Family
Table 2-8 shows the maximum number of multipliers for each member of the LatticeXP2 family. Table 2-9 shows the
maximum available EBR RAM Blocks and Serial TAG Memory bits in each LatticeXP2 device. EBR blocks, together
with Distributed RAM can be used to store variables locally for fast DSP operations.
Table 2-8. Maximum Number of DSP Blocks in the LatticeXP2 Family
Table 2-9. Embedded SRAM/TAG Memory in the LatticeXP2 Family
LatticeXP2 DSP Performance
Table 2-10 lists the maximum performance in Millions of MAC (MMAC) operations per second for each member of
the LatticeXP2 family.
Table 2-10. DSP Performance
For further information on the sysDSP block, please see TN1140, LatticeXP2 sysDSP Usage Guide.
XP2-17
XP2-30
XP2-40
Device
XP2-5
XP2-8
®
to support instantiation in the Simulink
XP2-17
XP2-30
XP2-40
Device
XP2-5
XP2-8
DSP Block
XP2-17
XP2-30
XP2-40
Device
XP2-5
XP2-8
3
4
5
7
8
EBR SRAM Block
12
15
21
48
9
9x9 Multiplier
®
DSP Block
tool, a graphical simulation environment. Simulink works with
2-25
24
32
40
56
64
3
4
5
7
8
Total EBR SRAM
(Kbits)
166
221
276
387
885
DSP Performance
18x18 Multiplier
LatticeXP2 Family Data Sheet
MMAC
10,400
3,900
5,200
6,500
9,100
12
16
20
28
32
TAG Memory
(Bits)
2184
2640
3384
632
768
36x36 Multiplier
Architecture
3
4
5
7
8