LFXP2-30E-5FN484C LATTICE SEMICONDUCTOR, LFXP2-30E-5FN484C Datasheet - Page 62

• Manufacturer Part Number: LFXP2-30E-5FN484C
• Description: IC, LATTICEXP2 FPGA, 435MHZ, FPBGA-484
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeXP2r

Specifications of LFXP2-30E-5FN484C

• No. Of Logic Blocks: 29000
• No. Of Macrocells: 14500
• Family Type: LatticeXP2
• No. Of Speed Grades: 5
• No. Of I/o's: 363
• Clock Management: PLL
• Total Ram Bits: 387Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP2 External Switching Characteristics (Continued)
t
DDR
t
t
t
t
f
f
Primary Clock
f
t
t
Edge Clock (ECLK1 and ECLK2)
f
t
t
1. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load.
2. DDR timing numbers based on SSTL25.
3. DDR2 timing numbers based on SSTL18.
Timing v. A 0.10
H_DELPLL
DVADQ
DVEDQ
DQVBS
DQVAS
MAX_DDR
MAX_DDR2
MAX_PRI
W_PRI
SKEW_PRI
MAX_ECLK
W_ECLK
SKEW_ECLK
Parameter
2
and DDR2
Clock to Data Hold - PIO Input
Register with Input Data Delay
Data Valid After DQS
(DDR Read)
Data Hold After DQS
(DDR Read)
Data Valid Before DQS
Data Valid After DQS
DDR Clock Frequency
DDR Clock Frequency
Frequency for Primary Clock Tree XP2
Clock Pulse Width for Primary
Clock
Primary Clock Skew Within a
Bank
Frequency for Edge Clock
Clock Pulse Width for Edge
Clock
Edge Clock Skew Within an Edge
of the Device
3
I/O Pin Parameters
Description
Over Recommended Operating Conditions
XP2-5
XP2-8
XP2-17
XP2-30
XP2-40
XP2
XP2
XP2
XP2
XP2
XP2
XP2
XP2
XP2
XP2
XP2
Device
3-18
Min.
0.00
0.00
0.00
0.00
0.00
0.71
0.25
0.25
133
95
—
—
—
—
—
1
1
-7
Max.
0.29
200
200
420
160
420
130
—
—
—
—
—
—
—
—
—
—
DC and Switching Characteristics
Min.
0.00
0.00
0.00
0.00
0.00
0.71
0.25
0.25
133
LatticeXP2 Family Data Sheet
—
95
—
—
—
—
1
1
-6
Max.
0.29
166
200
357
160
357
130
—
—
—
—
—
—
—
—
—
—
Min.
0.00
0.00
0.00
0.00
0.00
0.71
0.25
0.25
133
95
—
—
—
—
—
1
1
-5
Max.
0.29
133
166
311
160
311
130
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ps
ns
ps
UI
UI
UI
UI