EP3C16F484A7N Altera, EP3C16F484A7N Datasheet - Page 142

• Manufacturer Part Number: EP3C16F484A7N
• Description: Cyclone III
• Manufacturer: Altera

Specifications of EP3C16F484A7N

• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / Rohs Status: Compliant

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Software Overview
Cyclone III Device Handbook, Volume 1
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For more information about PCB layout guidelines, refer to
Layout Guidelines
Cyclone III device family high-speed I/O system interfaces are created in core logic
by a Quartus II software megafunction because they do not have a dedicated circuit
for the SERDES. The Cyclone III device family uses the I/O registers and LE registers
to improve the timing performance and support the SERDES. Altera Quartus II
software allows you to design your high-speed interfaces using the ALTLVDS
megafunction. This megafunction implements either a high-speed deserializer
receiver or a high-speed serializer transmitter. There is a list of parameters in the
ALTLVDS megafunction that you can set to customize your SERDES based on your
design requirements. The megafunction is optimized to use Cyclone III device family
resources to create high-speed I/O interfaces in the most effective manner.
When you are using the Cyclone III device family with the ALTLVDS megafunction,
the interface always sends the MSB of your parallel data first.
For more information about designing your high-speed I/O systems interfaces using
the ALTLVDS megafunction, refer to the
Quartus II
Use surface mount components.
Avoid 90° corners on board traces.
Use high-performance connectors.
Design backplane and card traces so that trace impedance matches the impedance
of the connector and termination.
Keep an equal number of vias for both signal traces.
Create equal trace lengths to avoid skew between signals. Unequal trace lengths
result in misplaced crossing points and decrease system margins as the
transmitter-channel-to-channel skew (TCCS) value increases.
Limit vias because they cause discontinuities.
Keep switching transistor-to-transistor logic (TTL) signals away from differential
signals to avoid possible noise coupling.
Do not route TTL clock signals to areas under or above the differential signals.
Analyze system-level signals.
Handbook.
and
AN 315: Guidelines for Designing High-Speed FPGA
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
ALTLVDS Megafunction User Guide
© December 2009 Altera Corporation
AN 224: High-Speed Board
PCBs.
Software Overview
and the