EP3C16F484A7N Altera, EP3C16F484A7N Datasheet - Page 242

• Manufacturer Part Number: EP3C16F484A7N
• Description: Cyclone III
• Manufacturer: Altera

Specifications of EP3C16F484A7N

• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / Rohs Status: Compliant

9–82
Dedicated Remote System Upgrade Circuitry
Cyclone III Device Handbook, Volume 1
This section explains the implementation of the Cyclone III device family remote
system upgrade dedicated circuitry. The remote system upgrade circuitry is
implemented in hard logic. This dedicated circuitry interfaces to the user-defined
factory application configurations implemented in the Cyclone III device family logic
array to provide the complete remote configuration solution. The remote system
upgrade circuitry contains the remote system upgrade registers, a watchdog timer,
and state machines that control those components.
the remote system upgrade block.
Figure 9–35. Remote System Upgrade Circuit Data Path
Notes to
(1) RU_DOUT, RU_SHIFTnLD, RU_CAPTnUPDT, RU_CLK, RU_DIN,RU_nCONFIG, and RU_nRSTIMER signals
(2) RU_CLK refers to ALTREMOTE_UPDATE megafunction block "clock" input. For more information, refer to the
are internally controlled by the ALTREMOTE_UPDATE megafunction.
Remote Update Circuitry (ALTREMOTE_UPDATE) Megafunction User
Previous
State
Register 2
Bit[30..0]
Figure
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
RU_DIN
9–35:
Status Register (SR)
Previous
State
Register 1
Bit[30..0]
din
RU_SHIFTnLD
Bit [40..39]
Logic
Current
State
Logic
Bit[31..0]
Shift Register
RU_CAPTnUPDT
dout
din
Logic Array
Bit [38..0]
Update Register
Bit [38..0]
Control Register
Bit [38..0]
Logic
clkout
capture
update
capture
dout
Logic
RU_CLK (2)
clkin
update
(Note 1)
Figure 9–35
Guide.
RU_DOUT
© December 2009 Altera Corporation
Internal Oscillator
RSU
Reconfiguration
State
Machine
RSU
Master
State
Machine
RU_nCONFIG
shows the data path of
Remote System Upgrade
timeout
RU_nRSTIMER
User
Watchdog
Timer