EP3C16F484A7N Altera, EP3C16F484A7N Datasheet - Page 34

• Manufacturer Part Number: EP3C16F484A7N
• Description: Cyclone III
• Manufacturer: Altera

Specifications of EP3C16F484A7N

• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / Rohs Status: Compliant

2–6
LAB Interconnects
LAB Control Signals
Cyclone III Device Handbook, Volume 1
The LAB local interconnect is driven by column and row interconnects and LE
outputs in the same LAB. Neighboring LABs, phase-locked loops (PLLs), M9K RAM
blocks, and embedded multipliers from the left and right can also drive the local
interconnect of a LAB through the direct link connection. The direct link connection
feature minimizes the use of row and column interconnects, providing higher
performance and flexibility. Each LE can drive up to 48 LEs through fast local and
direct link interconnects.
Figure 2–5
Figure 2–5. Cyclone III Device Family Direct Link Connection
Each LAB contains dedicated logic for driving control signals to its LEs. The control
signals include:
■
■
■
■
■
You can use up to eight control signals at a time. Register packing and synchronous
load cannot be used simultaneously.
Each LAB can have up to four non-global control signals. You can use additional LAB
control signals as long as they are global signals.
Synchronous clear and load signals are useful for implementing counters and other
functions. The synchronous clear and synchronous load signals are LAB-wide signals
that affect all registers in the LAB.
Two clocks
Two clock enables
Two asynchronous clears
One synchronous clear
One synchronous load
Direct link interconnect from
block, embedded multiplier,
shows the direct link connection.
left LAB, M9K memory
PLL, or IOE output
interconnect
Direct link
to left
Interconnect
Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
Local
LAB
© December 2009 Altera Corporation
Direct link
interconnect
to right
Direct link interconnect from
right LAB, M9K memory
block, embedded multiplier,
PLL, or IOE output
LAB Control Signals