EP3C16F484A7N Altera, EP3C16F484A7N Datasheet - Page 65

• Manufacturer Part Number: EP3C16F484A7N
• Description: Cyclone III
• Manufacturer: Altera

Specifications of EP3C16F484A7N

• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / Rohs Status: Compliant

Clock Networks
GCLK Network
© December 2009
CIII51006-3.2
f
Altera Corporation
This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)
with advanced features in the Cyclone
LS devices).
This chapter includes the following sections:
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The Cyclone III device family provides up to 16 dedicated clock pins (CLK[15..0])
that can drive the global clocks (GCLKs). The Cyclone III device family supports four
dedicated clock pins on each side of the device except EP3C5 and EP3C10 devices.
EP3C5 and EP3C10 devices only support four dedicated clock pins on the left and
right sides of the device.
For more information about the number of GCLK networks in each device density,
refer to the
GCLKs drive throughout the entire device, feeding all device quadrants. All resources
in the device (I/O elements, logic array blocks (LABs), dedicated multiplier blocks,
and M9K memory blocks) can use GCLKs as clock sources. Use these clock network
resources for control signals, such as clock enables and clears fed by an external pin.
Internal logic can also drive GCLKs for internally generated GCLKs and
asynchronous clears, clock enables, or other control signals with high fan-out.
“Clock Networks” on page 5–1
“PLLs in the Cyclone III Device Family” on page 5–9
“Cyclone III Device Family PLL Hardware Overview” on page 5–10
“Clock Feedback Modes” on page 5–12
“Hardware Features” on page 5–15
“Programmable Bandwidth” on page 5–22
“Phase Shift Implementation” on page 5–22
“PLL Cascading” on page 5–24
“PLL Reconfiguration” on page 5–24
“Spread-Spectrum Clocking” on page 5–32
“PLL Specifications” on page 5–32
Cyclone III Device Family Overview
5. Clock Networks and PLLs in the
®
III device family (Cyclone III and Cyclone III
chapter.
Cyclone III Device Family
Cyclone III Device Handbook, Volume 1