EP3C16F484A7N Altera, EP3C16F484A7N Datasheet - Page 225

• Manufacturer Part Number: EP3C16F484A7N
• Description: Cyclone III
• Manufacturer: Altera

Specifications of EP3C16F484A7N

• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
1
Altera Corporation
If JTAG programming fails to get the Cyclone III device family to enter user mode and
re-engage active programming, there are available methods to achieve this for the AS
or AP configuration schemes:
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■
ACTIVE_ENGAGE
The ACTIVE_ENGAGE instruction allows you to re-engage a disengaged active
controller. You can issue this instruction any time during configuration or user mode
to re-engage an already disengaged active controller as well as trigger reconfiguration
of the Cyclone III device family in the active configuration scheme specified by the
MSEL pin settings.
The ACTIVE_ENGAGE instruction functions as the PULSE_NCONFIG instruction when
the device is in passive configuration schemes (PS or FPP). The nCONFIG pin is
disabled when the ACTIVE_ENGAGE instruction is issued.
Altera does not recommend using the ACTIVE_ENGAGE instruction but it is provided
as a fail-safe instruction for re-engaging the active configuration (AS or AP)
controllers.
Overriding the Internal Oscillator
This feature is used for Cyclone III devices only and allows you to override the
internal oscillator during the active configuration scheme. The active configuration
(AS and AP) controllers use the internal oscillator as the clock source. You can change
the clock source to CLKUSR through JTAG instruction.
The EN_ACTIVE_CLK and DIS_ACTIVE_CLK JTAG instructions toggle on or off
whether the active clock is sourced from the CLKUSR pin or the internal configuration
oscillator. To source the active clock from the CLKUSR pin, issue the EN_ACTIVE_CLK
instruction. This causes the CLKUSR pin to become the active clock source. When
using the EN_ACTIVE_CLK instruction, the internal oscillator must be enabled for the
clock change to occur. By default, the configuration oscillator is disabled after
configuration and initialization is complete and the device has entered user mode.
However, the internal oscillator is enabled in user mode by either one of the following
conditions:
■
■
■
You must clock the CLKUSR pin at two times the expected DCLK frequency. The
CLKUSR pin allows a maximum frequency of 80 MHz (40 MHz DCLK). Normally, a test
instrument uses the CLKUSR pin when it wants to drive its own clock to control the AS
state machine.
When in the AS configuration scheme, you can re-engage the AS controller by
moving the JTAG TAP controller to the reset state or by issuing the
ACTIVE_ENGAGE instruction.
When in the AP configuration scheme, the only way to re-engage the AP controller
is to issue the ACTIVE_ENGAGE instruction. In this case, asserting the nCONFIG
pin does not re-engage either active controller.
A reconfiguration event (for example, driving nCONFIG low)
Remote update is enabled
Error detection is enabled
Cyclone III Device Handbook, Volume 1
9–65