EP3C16F484A7N Altera, EP3C16F484A7N Datasheet - Page 95

• Manufacturer Part Number: EP3C16F484A7N
• Description: Cyclone III
• Manufacturer: Altera

Specifications of EP3C16F484A7N

• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
© December 2009
Altera Corporation
Table 5–10
PHASECOUNTERSELECT setting.
Table 5–10. Phase Counter Select Mapping
To perform one dynamic phase shift step, you must perform the following
procedures:
1. Set phaseupdown and phasecounterselect as required.
2. Assert phasestep for at least two scanclk cycles. Each phasestep pulse
3. Deassert phasestep.
4. Wait for phasedone to go high.
5. You can repeat steps
All signals are synchronous to scanclk, so they are latched on the scanclk edges
and must meet t
Figure 5–24. PLL Dynamic Phase Shift
Dynamic phase shifting can be repeated indefinitely. All signals are synchronous to
scanclk, so they must meet t
enables one phase shift.
shifts.
PHASECOUNTERSELECT [2]
phasecounterselect
lists the PLL counter selection based on the corresponding
phaseupdown
0
0
0
0
1
1
1
SU
phasestep
phasedone
or t
scanclk
H
requirements (with respect to the scanclk edges).
1
through
SU
or t
4
H
as many times as required to get multiple phase
[1]
0
0
1
1
0
0
1
requirements (with respect to scanclk edges).
[0]
0
1
0
1
0
1
0
Cyclone III Device Handbook, Volume 1
All Output Counters
C0 Counter
C1 Counter
C2 Counter
C3 Counter
C4 Counter
M Counter
Selects
5–31