EP3C16F484A7N Altera, EP3C16F484A7N Datasheet - Page 85

Cyclone III

EP3C16F484A7N

Manufacturer Part Number
EP3C16F484A7N
Description
Cyclone III
Manufacturer
Altera
Datasheet

Specifications of EP3C16F484A7N

Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / Rohs Status
Compliant

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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Hardware Features
© December 2009
f
1
Altera Corporation
For more information about PLL software support in the Quartus II software, refer to
the
Guidelines
Use the following guidelines to design with clock switchover in PLLs:
Both inclk0 and inclk1 must be running when the clkswitch signal goes high to
start the manual clock switchover event. Failing to meet this requirement causes the
clock switchover to malfunction.
Figure 5–17. VCO Switchover Operating Frequency
Clock loss detection and automatic clock switchover requires that the inclk0 and
inclk1 frequencies be within 20% of each other. Failing to meet this requirement
causes the clkbad[0] and clkbad[1] signals to function improperly.
When using manual clock switchover, the difference between inclk0 and
inclk1 can be more than 20%. However, differences between the two clock
sources (frequency, phase, or both) can cause the PLL to lose lock. Resetting the
PLL ensures that the correct phase relationships are maintained between the input
and output clocks.
Applications that require a clock switchover feature and a small frequency drift
must use a low-bandwidth PLL. When referencing input clock changes, the
low-bandwidth PLL reacts slower than a high-bandwidth PLL. When the
switchover happens, the low-bandwidth PLL propagates the stopping of the clock
to the output slower than the high-bandwidth PLL. The low-bandwidth PLL
filters out jitter on the reference clock. However, you must be aware that the
low-bandwidth PLL also increases lock time.
After a switchover occurs, there may be a finite resynchronization period for the
PLL to lock onto a new clock. The exact amount of time it takes for the PLL to
re-lock is dependent on the PLL configuration.
If the phase relationship between the input clock to the PLL and output clock from
the PLL is important in your design, assert areset for 10 ns after performing a
clock switchover. Wait for the locked signal (or gated lock) to go high before
re-enabling the output clocks from the PLL.
Figure 5–17
clock is lost and then increases as the VCO locks on to the secondary clock. After
the VCO locks on to the secondary clock, some overshoot can occur (an
over-frequency condition) in the VCO frequency.
ALTPLL Megafunction User
ΔF vco
shows how the VCO frequency gradually decreases when the primary
Primary Clock Stops Running
Guide.
Switchover Occurs
Cyclone III Device Handbook, Volume 1
VCO Tracks Secondary Clock
Frequency Overshoot
5–21

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