EP3C16F484A7N Altera, EP3C16F484A7N Datasheet - Page 38

Cyclone III

EP3C16F484A7N

Manufacturer Part Number
EP3C16F484A7N
Description
Cyclone III
Manufacturer
Altera
Datasheet

Specifications of EP3C16F484A7N

Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484A7N
Manufacturer:
ALTERA
Quantity:
717
Part Number:
EP3C16F484A7N
Manufacturer:
ALTERA
0
Part Number:
EP3C16F484A7N
Manufacturer:
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Quantity:
20 000
3–2
Cyclone III Device Handbook, Volume 1
f
Table 3–1
Table 3–1. Summary of M9K Memory Features
For information about the number of M9K memory blocks for the Cyclone III device
family, refer to the
Configurations (depth × width)
Parity bits
Byte enable
Packed mode
Address clock enable
Single-port mode
Simple dual-port mode
True dual-port mode
Embedded shift register mode
ROM mode
FIFO buffer
Simple dual-port mixed width support
True dual-port mixed width support
Memory initialization file (.mif)
Mixed-clock mode
Power-up condition
Register asynchronous clears
Latch asynchronous clears
Write or read operation triggering
Same-port read-during-write
Mixed-port read-during-write
Notes to
(1) FIFO buffers and embedded shift registers that require external logic elements (LEs) for implementing control
(2) Width modes of ×32 and ×36 are not available.
logic.
Table
lists the features supported by the M9K memory
(1)
3–1:
Feature
Cyclone III Device Family Overview
(1)
(2)
Read address registers and output registers only
Chapter 3: Memory Blocks in the Cyclone III Device Family
Outputs set to Old Data or Don’t Care
Outputs set to Old Data or New Data
Write and read: Rising clock edges
chapter.
Output latches only
Outputs cleared
M9K Blocks
© December 2009 Altera Corporation
8192 × 1
4096 × 2
2048 × 4
1024 × 8
1024 × 9
512 × 16
512 × 18
256 × 32
256 × 36
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Overview

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