MT46H64M16LFBF-6 IT:B Micron Technology Inc, MT46H64M16LFBF-6 IT:B Datasheet - Page 5

• Manufacturer Part Number: MT46H64M16LFBF-6 IT:B
• Description: 64MX16 MOBILE DDR SDRAM PLASTIC IND TEMP GREEN VFBGA 1.8V
• Manufacturer: Micron Technology Inc

Specifications of MT46H64M16LFBF-6 IT:B

• Lead Free Status / RoHS Status: Compliant

List of Figures
Figure 1: 1Gb Mobile LPDDR Part Numbering .................................................................................................. 2
Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9
Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10
Figure 4: 60-Ball VFBGA – Top View, x16 only ................................................................................................. 11
Figure 5: 90-Ball VFBGA – Top View, x32 only ................................................................................................. 12
Figure 6: 152-Ball FBGA – 14mm x 14mm (Top View), x32 only ........................................................................ 13
Figure 7: 168-Ball FBGA – 12mm x 12mm (Top View), x32 only ........................................................................ 14
Figure 8: 60-Ball VFBGA (8mm x 9mm), Package Code: BF .............................................................................. 17
Figure 9: 90-Ball VFBGA (8mm x 13mm), Package Code: B5 ............................................................................ 18
Figure 10: 152-Ball WFBGA (14mm x 14mm), Package Code: MB ..................................................................... 19
Figure 11: 168-Ball WFBGA (12mm x 12mm), Package Code: MA ..................................................................... 20
Figure 12: Typical Self Refresh Current vs. Temperature ................................................................................. 30
Figure 13: ACTIVE Command ........................................................................................................................ 42
Figure 14: READ Command ........................................................................................................................... 43
Figure 15: WRITE Command ......................................................................................................................... 44
Figure 16: PRECHARGE Command ................................................................................................................ 45
Figure 17: DEEP POWER-DOWN Command .................................................................................................. 46
Figure 18: Simplified State Diagram ............................................................................................................... 52
Figure 19: Initialize and Load Mode Registers ................................................................................................. 54
Figure 20: Alternate Initialization with CKE LOW ............................................................................................ 55
Figure 21: Standard Mode Register Definition ................................................................................................ 56
Figure 22: CAS Latency .................................................................................................................................. 59
Figure 23: Extended Mode Register ................................................................................................................ 60
Figure 24: Status Read Register Timing .......................................................................................................... 62
Figure 25: Status Register Definition .............................................................................................................. 63
Figure 26: READ Burst ................................................................................................................................... 66
Figure 27: Consecutive READ Bursts .............................................................................................................. 67
Figure 28: Nonconsecutive READ Bursts ........................................................................................................ 68
Figure 29: Random Read Accesses ................................................................................................................. 69
Figure 30: Terminating a READ Burst ............................................................................................................. 70
Figure 31: READ-to-WRITE ............................................................................................................................ 71
Figure 32: READ-to-PRECHARGE .................................................................................................................. 72
Figure 33: Data Output Timing –
Figure 34: Data Output Timing –
Figure 35: Data Output Timing –
Figure 36: Data Input Timing ......................................................................................................................... 77
Figure 37: Write – DM Operation ................................................................................................................... 78
Figure 38: WRITE Burst ................................................................................................................................. 79
Figure 39: Consecutive WRITE-to-WRITE ....................................................................................................... 80
Figure 40: Nonconsecutive WRITE-to-WRITE ................................................................................................. 80
Figure 41: Random WRITE Cycles .................................................................................................................. 81
Figure 42: WRITE-to-READ – Uninterrupting ................................................................................................. 82
Figure 43: WRITE-to-READ – Interrupting ...................................................................................................... 83
Figure 44: WRITE-to-READ – Odd Number of Data, Interrupting .................................................................... 84
Figure 45: WRITE-to-PRECHARGE – Uninterrupting ...................................................................................... 85
Figure 46: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 86
Figure 47: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting ......................................................... 87
Figure 48: Bank Read – With Auto Precharge .................................................................................................. 90
Figure 49: Bank Read – Without Auto Precharge ............................................................................................. 91
Figure 50: Bank Write – With Auto Precharge .................................................................................................. 92
PDF: 09005aef83d9bee4
1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN
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QH, and Data Valid Window (x16) ................................................... 73
QH, and Data Valid Window (x32) ................................................... 74
DQSCK .......................................................................................... 75
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1Gb: x16, x32 Mobile LPDDR SDRAM
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