C8051F336-GMR Silicon Laboratories Inc, C8051F336-GMR Datasheet - Page 136

Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free

C8051F336-GMR

Manufacturer Part Number
C8051F336-GMR
Description
Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051F336-GMR

Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F336DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
10 bit
Package
20QFN
Device Core
8051
Family Name
C8051F336
Maximum Speed
25 MHz
Ram Size
768 Byte
Operating Temperature
-40 to 85 °C
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F336-GMR
Manufacturer:
SILICON
Quantity:
100
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Manufacturer:
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Quantity:
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Part Number:
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Quantity:
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Part Number:
C8051F336-GMR
0
C8051F336/7/8/9
SFR Definition 20.15. P2: Port 2
SFR Address = 0xA0; Bit Addressable
SFR Definition 20.16. P2MDIN: Port 2 Input Mode
SFR Address = 0xF3
136
Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices.
Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices.
Name
Reset
Name
Reset
7:5
4:0
7:4
3:0
Bit
Bit
Type
Type
Bit
Bit
UNUSED Unused.
P2MDIN[3:0]
P2[4:0]
Name
UNUSED
Name
R
R
7
0
7
0
Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Unused. Read = 0000b; Write = Don’t Care
Analog Configuration Bits for P2.3–P2.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
R
R
6
0
6
0
Description
R
R
5
0
5
0
Don’t Care
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
Rev.1.0
R
4
1
4
0
Function
Write
3
1
3
1
P2[4:0]
R/W
2
1
2
1
P2MDIN[7:0]
000b
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
R/W
1
1
1
1
Read
0
1
0
1

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