MPC8314ECVRADDA Freescale Semiconductor, MPC8314ECVRADDA Datasheet - Page 20

• Manufacturer Part Number: MPC8314ECVRADDA
• Description: MPU POWERQUICC II PRO 620-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8314ECVRADDA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DDR and DDR2 SDRAM
7.2.2
20
At recommended operating conditions
MCK[n] cycle time at MCK[n]/MCK[n] crossing
ADDR/CMD output setup with respect to MCK
ADDR/CMD output hold with respect to MCK
MCS[n] output setup with respect to MCK
MCS[n] output hold with respect to MCK
MCK to MDQS Skew
MDQ//MDM output setup with respect to MDQS
MDQ//MDM output hold with respect to MDQS
MDQS preamble start
MDQS epilogue end
Note:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (),
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
outputs (A) are setup (S) or output valid time. Also, t
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
control of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust
in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the
same adjustment value. See the MPC8315E PowerQUICC II Pro Host Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
symbol conventions described in note 1.
DDKHAS
symbolizes DDR timing (DD) for the time t
DDKHMH
DDR and DDR2 SDRAM Output AC Timing Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
follows the symbol conventions described in note 1. For example, t
MPC8314E PowerQUICC
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications
266 MHz
200 MHz
266 MHz
200 MHz
266 MHz
200 MHz
266 MHz
200 MHz
266 MHz
200 MHz
266 MHz
200 MHz
™
II Pro Processor Hardware Specifications, Rev. 0
MCK
DDKLDX
Symbol
t
t
t
t
t
t
t
t
t
t
t
DDKHMH
DDKHDS,
DDKHDX,
DDKHMP
DDKHME
DDKHCS
DDKHCX
DDKHAS
DDKHAX
DDKLDS
DDKLDX
memory clock reference (K) goes from the high (H) state until
t
MCK
symbolizes DDR timing (DD) for the time t
1
(first two letters of functional block)(signal)(state) (reference)(state)
for outputs. Output hold time can be read as DDR timing
–0.5 × t
1000
1100
1200
3.15
4.20
3.15
4.20
3.15
4.20
–0.6
–0.6
Min
900
7.5
2.9
3.5
MCK
– 0.6
DDKHMH
–0.5 × t
DDKHMH
Max
describes the DDR timing
0.6
0.6
10
—
—
—
—
—
—
—
—
—
—
—
—
MCK
can be modified through
Freescale Semiconductor
+ 0.6
DDKHMP
MCK
memory clock
Unit
follows the
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
Notes
for
2
3
3
3
3
4
5
5
6
6