MPC8314ECVRADDA Freescale Semiconductor, MPC8314ECVRADDA Datasheet - Page 95

• Manufacturer Part Number: MPC8314ECVRADDA
• Description: MPU POWERQUICC II PRO 620-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8314ECVRADDA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

23.2
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
not listed in
23.3
To simplify the PLL configurations, the MPC8314E might be separated into two clock domains. The first
domain contain the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The clock domains are independent, and each of their PLLs are
configured separately. Both of the domains has one common input clock.
configurations for 33, 25, and 66 MHz input clocks.
Freescale Semiconductor
Conf. No.
1
1
2
Core VCO frequency = core frequency × VCO divider.
0–1
nn
11
00
01
00
01
00
01
00
01
00
01
Suggested PLL Configurations
Core PLL Configuration
RCWL[COREPLL]
Table 72
SPMF
0100
0100
Core VCO frequency = core frequency × VCO divider
range of 400–800 MHz.
VCO divider has to be set properly so that the core VCO frequency is in the
nnnn
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
2–5
MPC8314E PowerQUICC
should be considered as reserved.
Table 72
Core\PLL
0000100
0000101
6
0
n
0
0
1
1
0
0
1
1
0
0
shows the encodings for RCWL[COREPLL]. COREPLL values that are
Table 73. Suggested PLL Configurations
Table 72. e300 Core PLL Configuration
(PLL off, csb_clk clocks core directly)
Input Clock Frequency (MHz) CSB Frequency (MHz) Core Frequency (MHz)
core_clk : csb_clk Ratio
™
II Pro Processor Hardware Specifications, Rev. 0
PLL bypassed
33.33
25
1.5:1
1.5:1
2.5:1
2.5:1
N/A
1:1
1:1
2:1
2:1
3:1
3:1
NOTE
(PLL off, csb_clk clocks core directly)
133.33
100
Table 73
VCO Divider
PLL bypassed
N/A
2
4
2
4
2
4
2
4
2
4
shows suggested PLL
1
266.66
250
Clocking
95