MPC8314ECVRADDA Freescale Semiconductor, MPC8314ECVRADDA Datasheet - Page 61

• Manufacturer Part Number: MPC8314ECVRADDA
• Description: MPU POWERQUICC II PRO 620-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8314ECVRADDA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.2
Table 53
16.3
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
16.4
Following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer please use the PCI Express
Base Specification, Rev. 1.0a.
16.4.1
Table 54
specified at the component pins.
Freescale Semiconductor
Unit interval
Differential peak-to-peak
output voltage
De-Emphasized
differential output voltage
(ratio)
Minimum TX eye width
Symbol
t
t
REFCJ
REFPJ
t
REF
Parameter
REFCLK cycle time
REFCLK cycle-to-cycle jitter. Difference in the period of any two
adjacent REFCLK cycles.
Phase jitter. Deviation in edge location with respect to mean edge
location.
defines the specifications for the differential output at all transmitters (TXs). The parameters are
lists the PCI Express SerDes clock AC requirements.
AC Requirements for PCI Express SerDes Clocks
Clocking Dependencies
Physical Layer Specifications
Differential Transmitter (TX) Output
MPC8314E PowerQUICC
Table 53. SD_REF_CLK and SD_REF_CLK AC Requirements
Table 54. Differential Transmitter (TX) Output Specifications
Parameter Description
V
V
TX-DE-RATIO
Symbol
TX-DIFFp-p
T
TX-EYE
UI
™
Each UI is 400 ps ± 300 ppm.
UI does not account for
Spread Spectrum Clock
dictated variations.
V
V
Ratio of the V
second and following bits after
a transition divided by the
V
a transition.
The maximum Transmitter
jitter can be derived as
T
0.3 UI.
II Pro Processor Hardware Specifications, Rev. 0
TX-MAX-JITTER
TX-DIFFp-p
TX-D-
TX-DIFFp-p
|
Comments
of the first bit after
= 2*|V
TX-DIFFp-p
= 1 - U
TX-D+
TX-EYE
of the
-
=
Min
–50
—
—
399.88
–3.0
0.70
Min
0.8
Typ
10
—
—
Typical
–3.5
400
—
—
Max
100
50
—
400.12
Max
-4.0
1.2
—
Units
Units
ns
ps
ps
dB
ps
UI
V
PCI Express
Notes
Notes
2, 3
—
—
—
1
2
2
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