MPC8314ECVRADDA Freescale Semiconductor, MPC8314ECVRADDA Datasheet - Page 32

• Manufacturer Part Number: MPC8314ECVRADDA
• Description: MPU POWERQUICC II PRO 620-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8314ECVRADDA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Ethernet: Three-Speed Ethernet, MII Management
9.5
Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes interface of
MPC8315E as shown in
output pin of the SerDes transmitter differential pair features 50-Ω output impedance. Each input of the
SerDes receiver differential pair features 50-Ω on-die termination to XCOREVSS. The reference circuit
of the SerDes transmitter and receiver is shown in
When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of
this eTSEC port can be left floating. The input signals should be terminated based on the guidelines
described in
the desired POR configuration requirement on these pins, if applicable.
When operating in SGMII mode, the TSEC_GTX_CLK125 clock is not required for this port. Instead,
SerDes reference clock is required on SD_REF_CLK and SD_REF_CLK pins.
9.5.1
The characteristics and DC requirements of the separate SerDes reference clock are described in
Section 15, “High-Speed Serial Interfaces (HSSI).”
9.5.2
Table 34
SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
32
Output clock to output valid
Timer alarm to output valid
Note:
1. The timer can operate on rtc_clock or tmr_clock. These clocks get muxed and any one of them can be selected.
2. Asynchronous signals.
3. Inputs need to be stable at least one TMR clock.
Symbol
t
t
REFCJ
REFPJ
t
REF
REFCLK cycle time
REFCLK cycle-to-cycle jitter. Difference in the period of any two
adjacent REFCLK cycles
Phase jitter. Deviation in edge location with respect to mean
edge location
lists the SGMII SerDes reference clock AC requirements. Please note that SD_REF_CLK and
SGMII Interface Electrical Characteristics
DC Requirements for SGMII SD_REF_CLK and SD_REF_CLK
AC Requirements for SGMII
Section 25.4, “Connection Recommendations,”
MPC8314E PowerQUICC
Parameter
Table 34. SD_REF_CLK and SD_REF_CLK AC Requirements
Figure
Parameter Description
Table 33. 1588 Timer AC Specifications (continued)
17, where C
™
II Pro Processor Hardware Specifications, Rev. 0
TX
is the external (on board) AC-Coupled capacitor. Each
Figure
SD_REF_CLK and SD_REF_CLK
Symbol
t
GCLKNV
t
TMRAL
48.
as long as such termination does not violate
Min
–50
—
-
Min
—
0
Typical
—
—
8
Max
—
Max
6
100
50
-
Freescale Semiconductor
Units
ps
ps
ns
Unit
ns
—
Notes
—
—
—
Notes
2