MPC8314ECVRADDA Freescale Semiconductor, MPC8314ECVRADDA Datasheet - Page 25

• Manufacturer Part Number: MPC8314ECVRADDA
• Description: MPU POWERQUICC II PRO 620-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8314ECVRADDA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 9
9.2.1.2
Table 26
Figure 10
Freescale Semiconductor
At recommended operating conditions with LVDD of 3.3 V ± 300 mv
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise V
RX_CLK clock fall time V
Note:
1. The symbols used for timing specifications herein follow the pattern of t
for inputs and t
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
(K) going to the high (H) state or setup time. Also, t
input signals (D) went invalid (X) relative to the t
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t
used with the appropriate letter: R (rise) or F (fall).
shows the MII transmit AC timing diagram.
provides the MII receive AC timing specifications.
provides the AC test load for eTSEC.
MII Receive AC Timing Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
TXD[3:0]
TX_CLK
Parameter/Condition
TX_EN
TX_ER
IL
MPC8314E PowerQUICC
(min) to V
IH
(max) to V
Output
IH
MRX
(max)
Table 26. MII Receive AC Timing Specifications
IL
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
Figure 9. MII Transmit AC Timing Diagram
t
(min)
MTXH
Figure 10. eTSEC AC Test Load
t
MTX
Z
™
0
MRX
II Pro Processor Hardware Specifications, Rev. 0
= 50 Ω
MRDXKL
clock reference (K) going to the low (L) state or hold time. Note that, in
symbolizes MII receive timing (GR) with respect to the time data
t
t
MTKHDX
t
MRXH
Symbol
MTXF
t
t
MRDVKH
MRDXKH
t
t
t
t
MRXR
MRXF
MRX
MRX
/t
MRX
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
1
R
t
L
MTXR
Ethernet: Three-Speed Ethernet, MII Management
= 50 Ω
10.0
10.0
Min
1.0
1.0
35
—
—
LVDD/2
Typ
400
40
—
—
—
—
—
MRDVKH
MRX
symbolizes MII
Max
4.0
4.0
65
—
—
—
—
clock reference
Unit
ns
ns
ns
ns
ns
ns
%
25