MPC8314ECVRADDA Freescale Semiconductor, MPC8314ECVRADDA Datasheet - Page 94

MPU POWERQUICC II PRO 620-PBGA

MPC8314ECVRADDA

Manufacturer Part Number
MPC8314ECVRADDA
Description
MPU POWERQUICC II PRO 620-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8314ECVRADDA

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
266MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
620-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8314ECVRADDA
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MPC8314ECVRADDA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Clocking
As described in
configuration word low and the CFG_SYS_CLKIN_DIV configuration input signal select the ratio
between the primary clock input (SYS_CLKIN or PCI_CLK) and the internal coherent system bus clock
(csb_clk).
csb_clk to SYS_CLKIN/PCI_SYNC_IN ratios.
94
Table 70
1
2
3
1
2
Section 23,
CFG_SYS_CLKIN_DIV
CFG_SYS_CLKIN_DIV
CFG_SYS_CLKIN_DIV select the ratio between SYS_CLKIN and PCI_SYNC_OUT.
SYS_CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
In the Host mode it does not matter if the value is High or Low.
CFG_SYS_CLKIN_DIV doubles csb_clk if set low.
SYS_CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
MPC8314E PowerQUICC
and
High/Low
at Reset
at Reset
High/Low
High/Low
High/Low
Table 71
High
High
High
High
Table 71. CSB Frequency Options for Agent Mode
“Clocking,” The LBIUCM, DDRCM, and SPMF parameters in the reset
Table 70. CSB Frequency Options for Host Mode
1
1
3
Table 69. System PLL Multiplication Factors
shows the expected frequency values for the CSB frequency for select
RCWL[SPMF]
0110–1111
0000
0001
0010
0011
0100
0101
SPMF
SPMF
0010
0011
0100
0101
0010
0011
0100
0101
II Pro Processor Hardware Specifications, Rev. 0
Input Clock
Input Clock
csb_clk :
csb_clk :
Multiplication Factor
Ratio
Ratio
2: 1
3: 1
4: 1
5: 1
2:1
3:1
4:1
5:1
System PLL
Reserved
Reserved
Reserved
2
2
× 2
× 3
× 4
× 5
120
120
24
96
25
Frequency (MHz)
frequency (MHz)
Input Clock
Input Clock
33.33
33.33
100
133
100
133
66.67
66.67
2
2
Freescale Semiconductor
133
133

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