MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 11

• Manufacturer Part Number: MC68LC060RC50
• Description: IC MPU 32BIT 68K 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

6.1.3.4
6.1.4
6.2
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
6.5
6.5.1
6.5.2
6.5.3
6.6
6.6.1
6.6.1.1
6.6.1.2
6.6.2
6.6.2.1
6.6.2.2
6.6.3
6.6.3.1
6.6.3.2
6.6.4
6.6.4.1
6.6.4.2
6.6.5
6.6.5.1
6.6.5.2
6.6.6
6.6.6.1
6.6.6.2
6.6.7
6.6.7.1
6.6.7.2
6.7
7.1
7.2
7.3
7.4
7.5
7.6
MOTOROLA
Floating-Point Data Formats and Data Types............................................... 6-7
Computational Accuracy ............................................................................. 6-11
Postprocessing Operation........................................................................... 6-15
Floating-Point Exceptions ........................................................................... 6-19
Floating-Point Arithmetic Exceptions .......................................................... 6-22
Floating-Point State Frames ....................................................................... 6-35
Bus Characteristics ....................................................................................... 7-1
Full-, Half-, and Quarter-Speed Bus Operation and BCLK ........................... 7-3
Acknowledge Termination Ignore State Capability ....................................... 7-4
Bus Control Register..................................................................................... 7-4
Data Transfer Mechanism............................................................................. 7-5
Misaligned Operands .................................................................................... 7-9
Floating-Point Instruction Address Register (FPIAR) ................................. 6-7
Intermediate Result................................................................................... 6-12
Rounding the Result ................................................................................. 6-13
Underflow, Round, and Overflow.............................................................. 6-15
Conditional Testing ................................................................................... 6-16
Unimplemented Floating-Point Instructions .............................................. 6-19
Unsupported Floating-Point Data Types................................................... 6-21
Unimplemented Effective Address Exception........................................... 6-22
Branch/Set on Unordered (BSUN)............................................................ 6-24
Signaling Not-a-Number (SNAN) .............................................................. 6-25
Operand Error ........................................................................................... 6-26
Overflow.................................................................................................... 6-28
Underflow.................................................................................................. 6-30
Divide-by-Zero .......................................................................................... 6-32
Inexact Result ........................................................................................... 6-33
Accrued Exception Byte ........................................................................... 6-6
Trap Disabled Results (FPCR BSUN Bit Cleared) ................................. 6-24
Trap Enabled Results (FPCR BSUN Bit Set) ......................................... 6-24
Trap Disabled Results (FPCR SNAN Bit Cleared) ................................. 6-25
Trap Enabled Results (FPCR SNAN Bit Set) ......................................... 6-26
Trap Disabled Results (FPCR OPERR Bit Cleared)............................... 6-27
Trap Enabled Results (FPCR OPERR Bit Set)....................................... 6-27
Trap Disabled Results (FPCR OVFL Bit Cleared) .................................. 6-29
Trap Enabled Results (FPCR OVFL Bit Set) .......................................... 6-29
Trap Disabled Results (FPCR UNFL Bit Cleared) .................................. 6-31
Trap Enabled Results (FPCR UNFL Bit Set) .......................................... 6-31
Trap Disabled Results (FPCR DZ Bit Cleared)....................................... 6-33
Trap Enabled Results (FPCR DZ Bit Set)............................................... 6-33
Trap Disabled Results (FPCR INEX1 Bit and INEX2 Bit Cleared........... 6-34
Trap Enabled Results (Either FPCR INEX1 Bit or INEX2 Bit Set).......... 6-34
M68060 USER’S MANUAL
Bus Operation
Section 7
Table of Contents
xiii