MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 309

• Manufacturer Part Number: MC68LC060RC50
• Description: IC MPU 32BIT 68K 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

10.3.2 Data ATC Miss
Assumptions:
Data ATC Miss = 8+3*w(3/0), if U-bit and M-bit of descriptor are in the proper state.
Data ATC Miss = 14+4*w(3/1), if M-bit only, or U-bit and M-bit of descriptor must be set by
the MC68060.
Data ATC Miss = 16+5*w(4/1), if U-bit only of descriptor must be set by the MC68060.
10.3.3 Instruction Cache Miss
Assumptions:
Instruction Cache Miss (Line Fill) = w+x+y+z
10.3.4 Data Cache Miss
Assumptions:
If copyback mode:
Data Cache Miss (Line Fill) = 2+w {+, if during x+y+z a memory data operand reference is
made by a subsequent instruction, an operand execution pipeline stall will take place until
the entire line is written into the data cache during x+y+z}
If noncachable mode (operand read):
Data Cache Miss = 2+w
If noncacheable mode (operand write) and precise mode or write buffer disabled:
Data Cache Miss = 3+w
MOTOROLA
• A single, “C-index” level, normal table search (the only U-bit or M-bit update possible is
• Given a memory response time of “w-x-y-z” to the bus interface of the MC68060.
• The following degradation time assumes the MC68060 instruction buffer is empty and
• The following degradation estimate assumes an instruction fetch flow of sequential op-
• Given a memory response time of “w-x-y-z” to the bus interface of the MC68060.
• Given a memory response time of “w-x-y-z” to the bus interface of the MC68060.
for the page descriptor itself).
the instruction cache miss memory access time is fully exposed. This is an estimated
degradation using a conservative assumption.
Note that the MC68060 instruction fetch pipeline prefetches continually, loading instruc-
tions into the instruction buffer, which decouples the instruction fetch pipeline from the
operand execution pipeline. As a result, instruction cache miss memory access times
for most operations will be partially or completely hidden by the instruction buffer, con-
tributing minimal degradation to actual execution time.
erations, the cache miss line is entered sequentially and contains no branches/jumps.
M68060 USER’S MANUAL
Instruction Execution Timing
10-13