MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 33

• Manufacturer Part Number: MC68LC060RC50
• Description: IC MPU 32BIT 68K 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

The MC68060 is compatible with the ANSI/IEEE Standard 754 for Binary Floating-Point
Arithmetic . The MC68060’s FPU has been optimized to execute the most commonly used
subset of the MC68881/MC68882 instruction sets. Software emulates floating-point instruc-
tions not directly supported in hardware. Refer to Appendix C MC68060 Software Pack-
age for details on software emulation. The MC68060FPSP provides the following features:
1.4.2.4 MEMORY UNITS. The MC68060 contains independent instruction and data mem-
ory units. Each memory unit consists of an 8-Kbyte cache, a cache controller, and an ATC.
The full addressing range of the MC68060 is 4 Gbytes. Even though most MC68060 sys-
tems implement a much smaller physical memory, by using virtual memory techniques, the
system can appear to have a full 4 Gbytes of memory available to each user program. Each
MMU fully supports demand-paged virtual-memory operating systems with either 4- or 8-
Kbyte page sizes. Each MMU protects supervisor areas from accesses by user programs
and provides write protection on a page-by-page basis. For maximum efficiency, each MMU
operates in parallel with other processor activities. The MMUs can be disabled for emulator
and debugging support.
1.4.2.5 ADDRESS TRANSLATION CACHES. The 64-entry, four-way, set-associative
ATCs store recently used logical-to-physical address translation information as page
descriptors for instruction and data accesses. Each MMU initiates address translation by
searching for a descriptor containing the address translation information in the ATC. If the
descriptor does not reside in the ATC, the MMU performs external bus cycles through the
bus controller to search the translation tables in physical memory. After being located, the
page descriptor is loaded into the ATC, and the address is correctly translated for the
access.
1.4.2.6 INSTRUCTION AND DATA CACHES. Studies have shown that typical programs
spend much of their execution time in a few main routines or tight loops. Earlier members of
the M68000 family took advantage of this locality-of-reference phenomenon to varying
degrees. The MC68060 takes further advantage of cache technology with its two, indepen-
dent, on-chip physical caches, one for instructions and one for data. The caches reduce the
processor's external bus activity and increase CPU throughput by lowering the effective
memory access time. For a typical system design, the large caches of the MC68060 yield a
very high hit rate, providing a substantial increase in system performance.
The autonomous nature of the caches allows instruction-stream fetches, data-stream
fetches, and external accesses to occur simultaneously with instruction execution. For
example, if the MC68060 requires both an instruction access and an external peripheral
access and if the instruction is resident in the on-chip cache, the peripheral access proceeds
unimpeded rather than being queued behind the instruction fetch. If a data operand is also
required and it is resident in the data cache, it can be accessed without hindering either the
instruction access or the external peripheral access. The parallelism inherent in the
MC68060 also allows multiple instructions that do not require any external accesses to exe-
MOTOROLA
• Arithmetic and Transcendental Instructions
• IEEE-Compliant Exception Handlers
• Unimplemented Data Type and Data Format Handlers
M68060 USER’S MANUAL
Introduction
1-9