MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 48

• Manufacturer Part Number: MC68LC060RC50
• Description: IC MPU 32BIT 68K 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Signal Description
2-2
Transfer Retry Acknowl-
edge
Transfer Error Acknowl-
edge
Transfer Cycle Burst In-
hibit
Transfer Cache Inhibit
Snoop Control
Bus Request
Bus Grant
Bus Grant Relinquish
Control
Bus Tenure Termination
Bus Busy
Cache Disable
MMU Disable
Reset In
Reset Out
Interrupt Priority Level
Interrupt Pending
Autovector
Processor Status
Processor Clock
Clock Enable
JTAG Enable
Test Clock
Test Mode Select
Test Data Input
Test Data Output
Test Reset
Thermal Resistor Con-
nections
Power Supply
Ground
Signal Name
PST4–PST0 Indicates internal processor status.
Mnemonic
IPL2–IPL0
THERM1,
THERM0
SNOOP
CLKEN
IPEND
RSTO
AVEC
JTAG
TRST
MDIS
CDIS
RSTI
BGR
V CC
GND
TRA
TMS
TDO
TEA
CLK
TCK
BTT
TBI
TCI
TDI
BR
BG
BB
Table 2-1. Signal Index (Continued)
Provides thermal sensing information.
Power supply.
Indicates the need to rerun the bus cycle.
Indicates an error condition exists for a bus transfer.
Indicates the slave cannot handle a line burst access.
Indicates the current bus transfer should not be cached.
Indicates the MC68060 should snoop bus activity while it is not the bus master.
Asserted by the processor to request bus mastership.
Asserted by an arbiter to grant bus mastership privileges to the processor.
Qualifies BG by indicating the degree of necessity for relinquishing bus owner-
ship when BG is negated.
Indicates the MC68060 has relinquished the bus in response to the external ar-
biter’s negation of BG.
Asserted by the current bus master to indicate it has assumed ownership of the
bus.
Dynamically disables the internal caches to assist emulator support.
Disables the translation mechanism of the MMUs.
Processor reset.
Asserted during execution of a RESET instruction to reset external devices.
Provides an encoded interrupt level to the processor.
Indicates an interrupt is pending.
Used during an interrupt acknowledge transfer to request internal generation of
the vector number.
Clock input used for all internal logic timing.
Defines the speed of the system bus clock to be full, 1/2, or 1/4 the speed of the
processor clock.
Selects between IEEE 1149.1 compliance operation and emulation mode oper-
ation.
Clock signal for the IEEE P1149.1 test access port (TAP).
Selects the principal operations of the test-support circuitry.
Serial data input for the TAP.
Serial data output for the TAP.
Provides an asynchronous reset of the TAP controller.
Ground connection.
M68060 USER’S MANUAL
Function
MOTOROLA