MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 253

• Manufacturer Part Number: MC68LC060RC50
• Description: IC MPU 32BIT 68K 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

8.4.4 Eight-Word Stack Frame (Format $4)
An eight-word stack frame is created for data and instruction access errors. It is also used
for the floating-point disabled exception. Refer to 8.2.4 Illegal Instruction and Unimple-
mented Instruction Exceptions for details on the use of this frame for the floating-point dis-
abled exception. The following paragraphs describe in detail the format for this frame as
used by for the access error and how the processor uses it when returning from exception
processing.
8.4.4.1 Program Counter (PC). On read access faults, the PC points to the instruction that
caused the access error. This instruction is restarted when an RTE is executed, hence, the
read cycle is re-executed. On read access errors on the second or later of misaligned reads,
the read cycles that are successful prior to the access error are re-executed since the pro-
cessor uses a restart model for recovery from exceptions.
Programs that rely on a read bus error to test for the existence of I/O or peripheral devices
must increment the value of the PC prior to the execution of the RTE instruction. Increment-
ing the PC involves the calculation of the instruction length, which is dependent on the
addressing mode used. To avoid having to calculate the instruction length, it is possible to
use a NOP-TEST_WRITE-NOP instead of a TEST_READ of the I/O or peripheral device.
The initial NOP causes all prior write cycles to complete. The TEST_WRITE causes the
access error, and if the write cycle is to imprecise operand space, the stacked PC of the
access error stack contains the address of the second NOP. When the RTE is executed,
instruction execution resumes at the second NOP. The limitation of this method is that it
works only if the I/O device is mapped to imprecise operand space. If the write is to a precise
operand space, the processor does not increment the PC, and the stacked PC contains the
instruction address of the TEST_WRITE.
On write access errors, the PC points to the instruction that causes the access error except
for bus error (TEA) on writes that involve the push and store buffers. Refer to 8.4.4.3 Fault
Status Long Word (FSLW) for specific information on these write cases. For these write
cases, the PC does not point to the instruction that caused the access error. Hence the write
cycle that incurred the bus error is lost. In general, bus errors on writes must be avoided.
The processor provides little support for recovery on bus errored write cycles to imprecise
operand spaces. For precise spaces, both the faulting PC and logical operand address are
directly provided in the exception frame.
MOTOROLA
SP
+$02
+$06
+$08
+$0C
* Defined for the Floating-Point Disabled Exception
15
0 1 0 0
EIGHT-WORD STACK FRAME–FORMAT $4
FAULT STATUS LONGWORD (FSLW) or
Stack Frames
PC OF FAULTED INSTRUCTION*
EFFECTIVE ADDRESS*
PROGRAM COUNTER
FAULT ADDRESS or
STATUS REGISTER
VECTOR OFFSET
M68060 USER’S MANUAL
0
• Data or Instruction Access
• Floating-Point Disabled Ex-
Fault (ATC Fault or Bus Er-
ror)
ception
Exception Types
• See 8.4.4.1 Program
• Next instruction; Effective
Counter (PC), 8.4.4.2 Fault
Address, and 8.4.4.3 Fault
Status Long Word (FSLW)
for additional information.
Address Field has calculated
<ea> of memory operand (if
any); PC of Faulted Instruc-
tion points to the F-line in-
struction word of the floating-
point instruction.
Stacked PC Points To
Exception Processing
8-21