MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 76

• Manufacturer Part Number: MC68LC060RC50
• Description: IC MPU 32BIT 68K 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

CM—Cache Mode
W—Write Protect
Bits 4,3,1,0—Reserved by Motorola.
4.2 LOGICAL ADDRESS TRANSLATION
The primary function of the MMUs is to translate logical addresses to physical addresses.
The MMUs perform translations according to control information in translation tables. The
operating system creates these translation tables and stores them in memory. The proces-
sor then searches through a translation table as needed and stores the resulting translation
in an ATC.
4.2.1 Translation Tables
Both instruction and data access use the same translation tree. Separate translations trees
are available for user and supervisor accesses.
Figure 4-6 illustrates the three-level tree structure of a general translation table supported
by the MC68060. The root- and pointer-level tables contain the base addresses of the tables
at the next level. The page-level tables contain either the physical address for the translation
or a pointer to the memory location containing the physical address. Only a portion of the
translation table for the entire logical address space is required to be resident in memory at
any time—specifically, only the portion of the table that translates the logical addresses of
the currently executing process. Portions of translation tables can be dynamically allocated
as the process requires additional memory.
The current privilege mode determines the use of the URP or SRP for translation of the
access. The root pointer contains the base address of the translation table’s root-level table.
The translation table consists of several linked tables of descriptors. The table descriptors
of the root- and pointer-levels can have resident or invalid descriptor types. The page
descriptors of the page-level table have resident, indirect, or invalid descriptor types. The
page descriptors of the page-level table can be resident, indirect, or invalid. A page descrip-
tor defines the physical address of a page frame in memory that corresponds to the logical
address of a page. An indirect descriptor, which contains a pointer to the actual page
MOTOROLA
from an access. These bits can be programmed by the user to support external address-
ing, bus snooping, or other applications.
This field selects the cache mode and access precision as follows:
Section 5 Caches provides detailed information on caching modes.
This bit indicates the write privilege of the TTR block.
00 = Cachable, Writethrough
01 = Cachable, Copyback
10 = Cache-Inhibited, Precise Exception Model
11 = Cache-Inhibited, Imprecise Exception Model
0 = Read and write accesses permitted
1 = Write accesses not permitted
M68060 USER’S MANUAL
Memory Management Unit
4-7