MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 315

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MC68LC060RC50

Manufacturer Part Number
MC68LC060RC50
Description
IC MPU 32BIT 68K 50MHZ 206-PGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68LC060RC50

Processor Type
M680x0 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
206-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
10.9 SHIFT/ROTATE EXECUTION TIMES
Table 10-13 indicates the number of clock cycles required for execution of the shift and
rotate instructions. The number of operand read and write cycles is shown in parentheses
(r/w). Where indicated, the number of clock cycles and r/w cycles must be added to those
required for effective address calculation.
10.10 BIT MANIPULATION AND BIT FIELD EXECUTION TIMES
Table 10-14 and Table 10-15 indicate the number of clock cycles required for execution of
the bit manipulation instructions. The execution times for the bit field instructions is shown
in Table 10-16. The number of operand read and write cycles is shown in parentheses (r/w).
Where indicated, the number of clock cycles and r/w cycles must be added to those required
for effective address calculation.
MOTOROLA
1
For entries in this column, add the effective address calculation time. These operations
are word-size only.
ROXL, ROXR
Instruction
ROL, ROR
ASL, ASR
LSL, LSR
Table 10-14. Bit Manipulation (Dynamic Bit Count)
1
For entries in this column, add the effective address calculation
time.
Instruction
Table 10-13. Shift/Rotate Execution Times
BCHG
BCLR
BSET
BTST
M68060 USER’S MANUAL
Execution Times
Byte, Word
Byte, Word
Byte, Word
Byte, Word
Long
Long
Long
Long
Byte
Byte
Byte
Byte
Size
Long
Long
Long
Long
Size
Register
1(0/0)
1(0/0)
1(0/0)
1(0/0)
Register
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
Memory
1(1/1)
1(1/1)
1(1/1)
1(1/0)
Instruction Execution Timing
Memory
1
1(1/1)
1(1/1)
1(1/1)
1(1/1)
1
10-19

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