MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 9

• Manufacturer Part Number: MC68LC060RC50
• Description: IC MPU 32BIT 68K 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

3.1
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
3.2.1.4
3.2.1.5
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.2.4
3.2.2.5
4.1
4.1.1
4.1.2
4.1.3
4.2
4.2.1
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.3
4.2.4
4.2.4.1
4.2.4.2
4.2.4.3
4.2.4.4
4.2.5
4.2.6
4.2.6.1
4.2.6.2
4.2.6.3
4.3
4.4
4.5
4.6
4.6.1
MOTOROLA
Integer Unit Execution Pipelines ................................................................... 3-1
Integer Unit Register Description .................................................................. 3-2
Memory Management Programming Model.................................................. 4-3
Logical Address Translation.......................................................................... 4-7
Address Translation Caches....................................................................... 4-24
Transparent Translation.............................................................................. 4-27
Address Translation Summary.................................................................... 4-28
RSTI and MDIS Effect on the MMU ............................................................ 4-28
Integer Unit User Programming Model ....................................................... 3-2
Integer Unit Supervisor Programming Model.............................................. 3-3
User and Supervisor Root Pointer Registers .............................................. 4-3
Translation Control Register ....................................................................... 4-4
Transparent Translation Registers ............................................................. 4-6
Translation Tables ...................................................................................... 4-7
Descriptors................................................................................................ 4-12
Translation Table Example ....................................................................... 4-15
Variations in Translation Table Structure.................................................. 4-16
Table Search Accesses ............................................................................ 4-19
Address Translation Protection................................................................. 4-20
Effect of RSTI on the MMUs ..................................................................... 4-28
Data Registers (D7–D0) ........................................................................... 3-2
Address Registers (A6–A0) ...................................................................... 3-2
User Stack Pointer (A7) ............................................................................ 3-2
Program Counter ...................................................................................... 3-3
Condition Code Register .......................................................................... 3-3
Supervisor Stack Pointer .......................................................................... 3-4
Status Register ......................................................................................... 3-4
Vector Base Register................................................................................ 3-4
Alternate Function Code Registers........................................................... 3-5
Processor Configuration Register............................................................. 3-5
Table Descriptors.................................................................................... 4-12
Page Descriptors .................................................................................... 4-12
Descriptor Field Definitions..................................................................... 4-13
Indirect Action ......................................................................................... 4-16
Table Sharing Between Tasks................................................................ 4-17
Table Paging .......................................................................................... 4-17
Dynamically Allocated Tables................................................................. 4-17
Supervisor and User Translation Tables ................................................ 4-21
Supervisor Only ...................................................................................... 4-22
Write Protect ........................................................................................... 4-22
Memory Management Unit
M68060 USER’S MANUAL
Integer Unit
Section 3
Section 4
Table of Contents
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