MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 151

• Manufacturer Part Number: MC68LC060RC50
• Description: IC MPU 32BIT 68K 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

6.6.6.1 TRAP DISABLED RESULTS (FPCR DZ BIT CLEARED). The destination floating-
point data register is written with a result that is dependent on the instruction that caused the
DZ exception.
6.6.6.2 TRAP ENABLED RESULTS (FPCR DZ BIT SET). The destination floating-point
data register is not modified. Control is passed to the user DZ handler as a pre-instruction
exception when the next floating-point instruction is encountered. The user DZ handler must
generate a result to store in the destination.
The user DZ handler must execute an FSAVE instruction as the first floating-point instruction
to prevent further exceptions from reporting. The address of the instruction that causes the
overflow is available to the user DZ handler in the FPIAR. By examining the instruction, the
user DZ handler can determine the arithmetic operation type and destination location. The
exception operand is stored in the floating-point state frame (generated by the FSAVE). The
exception operand contains the source operand converted to the extended-precision format.
When the user DZ exception handler has completed, the floating-point frame may be dis-
carded. The RTE instruction must be executed to return to normal instruction flow.
6.6.7 Inexact Result
The processor provides two inexact bits in the FPSR EXC byte to help distinguish between
inexact results generated by emulated decimal input (INEX1 exceptions) and other inexact
results (INEX2 exceptions). These two bits are useful in instructions where both types of
inexact results can occur (e.g., FDIV.P #7E-1,FP3). In this case, the packed decimal to
extended-precision conversion of the immediate source operand causes an inexact error to
occur that is signaled as INEX1 exception. Furthermore, the subsequent divide could also
produce an inexact result and cause INEX2 to be set in the FPCR EXC byte. Note that only
one inexact exception vector number is generated by the processor. If either of the two inex-
act exceptions is enabled, the processor fetches the inexact exception vector, and the user
INEX exception handler is initiated. INEX refers to both exceptions in the following para-
graphs.
MOTOROLA
1. For the FDIV and FSGLDIV instructions, an infinity with the sign set to the exclusive
2. For the FLOGx instructions, a
3. For the FATANH instruction, a + is stored in the destination if the source operand is
OR of the signs of the input operands is stored in the destination.
a –1, otherwise, a – is stored in the destination if the source operand is +1.
Instruction
FLOGNP1
FSGLDIV
FATANH
FLOG10
FLOGN
FLOG2
FTAN
FDIV
Table 6-15. Possible Divide-by-Zero Exceptions
Source operand = 0 and floating-point data register is not a NAN, , or zero
Source operand = 0
Source operand = 0
Source operand = 0
Source operand is an odd multiple of
Source operand = 0 and floating-point data register is not a NAN, , or zero
Source operand = 1
Source operand = –1
M68060 USER’S MANUAL
–
is stored in the destination.
Operand Value
2
Floating-Point Unit
6-33