MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 95

• Manufacturer Part Number: MC68LC060RC50
• Description: IC MPU 32BIT 68K 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Memory Management Unit
U0, U1—User Page Attributes
V—Valid
W—Write Protected
For each access to a memory unit, the MMU uses the four bits of the logical address located
just above the page offset (LA16–LA13 for 8K pages, LA15–LA12 for 4K pages) to index
into the ATC. The tags are compared with the remaining upper bits of the logical address
and FC2. If one of the tags matches and is valid, then the multiplexer chooses the corre-
sponding entry to produce the physical address and status information. The ATC outputs
the corresponding physical address to the cache controller, which accesses the data within
the cache and/or requests an external bus cycle. Each ATC entry contains a logical address,
a physical address, and status bits.
When the ATC does not contain the translation for a logical address, a miss occurs. The
MMU aborts the current access and searches the translation tables in memory for the cor-
rect translation. If the table search completes without any errors, the MMU stores the trans-
lation in the ATC and provides the physical address and attributes for the access. Otherwise,
if any bus errors (TEA asserted) or invalid descriptors are encountered, the ATC is not mod-
ified and an access error exception is taken. The MC68040 differs from the MC68060 in that
the MC68040 ATC contains an R-bit. An R-bit is not needed on the MC68060 because the
ATC is not updated when an access error occurs and therefore all ATC entries represent
usable translations.
There are some variations in the logical-to-physical mapping because of the two page sizes.
If the page size is 4 Kbytes, then logical address bit 12 is used to access the ATC's memory,
the tag comparators use bit 16, and physical address bit 12 is an ATC output. If the page
size is 8 Kbytes, then logical address bit 16 is used to access the ATC's memory, and phys-
ical address bit 12 is driven by logical address bit 12. It is advisable that a translation always
be disabled before changing size and that the ATCs are flushed before enabling translation
again.
The MMU is organized such that other operations always completely overlap the translation
time of the ATCs; thus, no performance penalty is associated with ATC searches. The
address translation occurs in parallel with indexing into the on-chip instruction and data
caches.
4-26
These user-defined bits are not interpreted by the MC68060. U0 and U1 are echoed to
the UPA0 and UPA1 signals, respectively, if an external bus transfer results from the
access.
When set, this bit indicates that the entry is valid. This bit is set when the MC68060 loads
an entry. A flush operation by a PFLUSH or PFLUSHA instruction that selects this entry
clears the bit.
This write-protect bit is set when a W-bit is set in any of the descriptors encountered dur-
ing the table search for this entry. Setting a W-bit in a table descriptor write protects all
pages accessed with that descriptor. When the W-bit is set, a write access or a locked
read-modify-write access to the logical address corresponding to this entry causes an
access error exception to be taken immediately.
M68060 USER’S MANUAL
MOTOROLA