AD9852ASVZ Analog Devices Inc, AD9852ASVZ Datasheet - Page 18

• Manufacturer Part Number: AD9852ASVZ
• Description: IC DDS SYNTHESIZER CMOS 80-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9852ASVZ

• Resolution (bits): 12 b
• Master Fclk: 300MHz
• Tuning Word Width (bits): 48 b
• Voltage - Supply: 3.14 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Transmitting Current: 815mA
• Rf Ic Case Style: TQFP
• No. Of Pins: 80
• Supply Voltage Range: 3.135V To 3.465V
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 3 - 168 Hours
• Frequency Max: 300MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9852/PCBZ - BOARD EVAL FOR AD9852
• Lead Free Status / Rohs Status: Compliant

AD9852
MODES OF OPERATION
There are five programmable modes of operation of the AD9852.
Selecting a mode requires that three bits in the control register
(Parallel Address 1F hex) be programmed as shown in Table 6.
Table 6. Mode Selection Table
Mode 2
0
0
0
0
1
In each mode, engaging certain functions may be prohibited.
Table 7 lists some important functions and their availability for
each mode.
SINGLE TONE (MODE 000)
When the MASTER RESET pin is asserted, single-tone mode
becomes the default. The user can also access this mode by
programming it into the control register. The phase accumulator,
responsible for generating an output frequency, is presented with
a 48-bit value from the Frequency Tuning Word 1 registers with
default values of 0. Default values from the remaining applicable
registers further define the single-tone output signal qualities.
The default values after a master reset configures the device
with an output signal of 0 Hz and zero phase. Upon power-up
and reset, the output from both DACs is a dc value equal to the
midscale output current. This is the default mode amplitude setting
of 0. Refer to the On/Off Output Shaped Keying (OSK) section
for further explanation of the output amplitude control. It is
necessary to program all or some of the 28 program registers to
produce a user-defined output signal. Figure 32 shows the
transition from the default condition (0 Hz) to a user-defined
output frequency (F1).
Mode 1
0
0
1
1
0
MASTER RESET
I/O UD CLK
Mode 0
0
1
0
1
0
MODE
FREQUENCY
TW1
000 (DEFAULT)
F1
0
0
Result
Single tone
FSK
Ramped FSK
Chirp
BPSK
Figure 32. Default State to User-Defined Output Transition
Rev. E | Page 18 of 52
000 (SINGLE TONE)
As with all Analog Devices DDS devices, the value of the frequency
tuning word is determined using the following equation:
where:
N is the phase accumulator resolution (48 bits in this instance).
Desired Output Frequency is expressed in hertz.
FTW (frequency tuning word) is a decimal number.
After a decimal number has been calculated, it must be rounded
to an integer and then converted to binary format—a series of
48 binary-weighted 1s and 0s. The fundamental sine wave DAC
output frequency range is from dc to one-half SYSCLK.
Changes in frequency are phase continuous; therefore, the first
sampled phase value of the new frequency is referenced from the
time of the last sampled phase value of the previous frequency.
The 14-bit phase register adjusts the cosine DAC’s output phase.
The single-tone mode allows the user to control the following
signal qualities:
•
•
•
Furthermore, all of these qualities can be changed or modulated
via the 8-bit parallel programming port at a 100 MHz parallel
byte rate or at a 10 MHz serial rate. Incorporating this attribute
permits FM, AM, PM, FSK, PSK, and ASK operation in the
single-tone mode.
F1
FTW = (Desired Output Frequency × 2
•
•
•
Output frequency to 48-bit accuracy
Output amplitude to 12-bit accuracy
Output phase to 14-bit accuracy
Fixed, user-defined amplitude control
Variable, programmable amplitude control
Automatic, programmable, single-pin-controlled
on/off output shaped keying
N
)/SYSCLK