AD9852ASVZ Analog Devices Inc, AD9852ASVZ Datasheet - Page 36

• Manufacturer Part Number: AD9852ASVZ
• Description: IC DDS SYNTHESIZER CMOS 80-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9852ASVZ

• Resolution (bits): 12 b
• Master Fclk: 300MHz
• Tuning Word Width (bits): 48 b
• Voltage - Supply: 3.14 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Transmitting Current: 815mA
• Rf Ic Case Style: TQFP
• No. Of Pins: 80
• Supply Voltage Range: 3.135V To 3.465V
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 3 - 168 Hours
• Frequency Max: 300MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9852/PCBZ - BOARD EVAL FOR AD9852
• Lead Free Status / Rohs Status: Compliant

AD9852
CONTROL REGISTER DESCRIPTIONS
The control register is located at Address 1D hex to Address 20 hex (shown in the shaded portion of Table 9). It is composed of 32 bits.
Bit 31 is located at the top left position, and Bit 0 is located in the lower right position of the shaded area of Table 9. The register has been
subdivided into bits to make it easier to locate the information associated with specific control categories.
Table 13. Control Register Bit Descriptions
Bit
CR [31:29]
CR [28]
CR [27]
CR [26]
CR [25]
CR [24]
CR [23]
CR [22]
CR [21]
CR [20:16]
CR [15]
CR [14]
CR [13]
CR [12]
CR [11:9]
CR [8]
CR [7]
CR [6]
CR [5]
CR [4]
CR [3:2]
CR [1]
CR [0]
Description
Open.
The comparator power-down bit. When this bit is set to Logic 1, it indicates to the comparator that a power-down mode is
active. This bit is an output of the digital section and is an input to the analog section.
Must always be written to Logic 0. Writing this bit to Logic 1 causes the AD9852 to stop functioning until a master reset is applied.
The control DAC power-down bit. When this bit is set to Logic 1, it indicates to the control DAC that power-down mode is active.
The full DAC power-down bit. When this bit is set to Logic 1, it indicates to both the cosine and control DACs, as well as the
reference, that a power-down mode is active.
The digital power-down bit. When this bit is set to Logic 1, it indicates to the digital section that a power-down mode is
active. Within the digital section, the clocks are forced to dc, effectively powering down the digital section. The PLL still
accepts the REFCLK signal and continues to output the higher frequency.
Reserved. Write to 0.
The PLL range bit. The PLL range bit controls the VCO gain. The power-up state of the PLL range bit is Logic 1; a higher gain is
required for frequencies greater than 200 MHz.
The bypass PLL bit, active high. When this bit is active, the PLL is powered down and the REFCLK input is used to drive the
system clock signal. The power-up state of the bypass PLL bit is Logic 1 with PLL bypassed.
The PLL multiplier factor. These bits are the REFCLK multiplication factor unless the bypass PLL bit is set. The PLL multiplier
valid range is from 4 to 20, inclusive.
The Clear Accumulator 1 bit. This bit has a one-shot type of function. When this bit is written active (Logic 1), a Clear
Accumulator 1 signal is sent to the DDS logic, resetting the accumulator value to 0. The bit is then automatically reset, but
the buffer memory is not reset. This bit allows the user to easily create a sawtooth frequency sweep pattern with minimal
user intervention. This bit is intended for chirp mode only, but its function is still retained in other modes.
The clear accumulator bit. When this bit is active high, it holds both the Accumulator 1 and Accumulator 2 values at 0 for as
long as the bit is active. This allows the DDS phase to be initialized via the I/O port.
The triangle bit. When this bit is set, the AD9852 automatically performs a continuous frequency sweep from F1 to F2
frequencies and back. The effect is a triangular frequency sweep. When this bit is set, the operating mode must be set to
ramped FSK.
Don’t care.
The three bits that describe the five operating modes of the AD9852:
0x0 = single-tone mode
0x1 = FSK mode
0x2 = ramped FSK mode
0x3 = chirp mode
0x4 = BPSK mode
The internal update active bit. When this bit is set to Logic 1, the I/O UD CLK pin is an output and the AD9852 generates the
I/O UD CLK signal. When this bit is set to Logic 0, external I/O update function is performed, and the I/O UD CLK pin is
configured as an input.
Reserved. Write to 0.
This is the inverse sinc filter bypass bit. When this bit is set, the data from the DDS block goes directly to the output shaped
keying logic, and the clock for the inverse sinc filter is stopped. Default is clear with the filter enabled.
The output shaped keying enable bit. When this bit is set, the output ramping function is enabled and is performed in
accordance with the CR [4] bit requirements.
The internal/external output shaped keying control bit. When this bit is set to Logic 1, the output shaped keying factor is
internally generated and applied to the cosine DAC path. When this bit is cleared (default), the output shaped keying function is
externally controlled by the user, and the output shaped keying factor is the value of the output shaped keying multiplier
register. The two output shaped keying multiplier registers also default low so that the output is off at power-up until the device
is programmed by the user.
Reserved. Write to 0.
The serial port MSB-/LSB-first bit. Defaults low, MSB first.
The serial port SDO active bit. Defaults low, inactive.
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